36 / 58 page
DM9601
USB to Ethernet MAC Controller with Integrated 10/100 PHY
36
Final
Version: DM9601-DS-F01
June 22, 2002
If this bit is 1, it means the operation 1 mode is a 10M half duplex
mode. The software can read bit[15:12] to see which mode is
selected after auto-negotiation. This bit is invalid when it is not in the
auto-negotiation mode
17.11-
17.9
RESERVED
0, RO
Reserved
Write as 0, ignore on read
17.8-17.4 PHYADR[4:0]
(PHYADR),
RW
PHY Address Bit 4:0
The first PHY address bit transmitted or received is the MSB of the
address (bit 4). A station management entity connected to multiple
PHY entities must know the appropriate address of each PHY
17.3-17.0
ANMB[3:0]
0, RO
Auto-negotiation Monitor Bits
These bits are for debug only. The auto-negotiation status will be
written to these bits
B3 b2 b1 B0
0
0
0
0
In IDLE state
000
1
Ability match
0
0
1
0
Acknowledge match
0
0
1
1
Acknowledge match fail
0
1
0
0
Consistency match
0
1
0
1
Consistency match fail
0
1
1
0
Parallel detects signal_link_ready
0
1
1
1
Parallel detects signal_link_ready fail
1
0
0
0
Auto-negotiation completed successfully
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
