DM9601
USB to Ethernet MAC Controller with Integrated 10/100 PHY
Final
25
Version: DM9601-DS-F01
June 22, 2002
10.19 General purpose Register ( 1FH )
Bit
Name
Default
Description
7
RESERVED
0,RO
Reserved
6:1
GEPIO6-1
0,RW
General Purpose
When the correspondent bit of General Purpose Control Register is 1, the value of
the bit is output to pin GEPIO6-1
When the correspondent bit of General Purpose Control Register is 0, the value of
the bit be read is reflected from correspondent pins of GEPIIO6-1
The GEPIOs are mapped to pins GEPIO6 to GEPIO1 respectively
0
GEPIO0
1,RW
General Purpose
When the correspondent bit of General Purpose Control Register is 1, the value of
the bit is output to pin GEPIO0
When the correspondent bit of General Purpose Control Register is 0, the value of
the bit be read is reflected from pin GEPIO0
GEPIO0 default output 1 to POWER_DOWN internal PHY. Driver need to clear this
POWER_DOWN signal by write “0” when it wants PHY active. If other device need,
it also can refer this signal. This default value can be programmed by EEPROM.
Please refer EEPROM description
10.20 TX SRAM Write Pointer Address Register (20H~21H)
Bit
Name
Default
Description
7:0
TWPAH
00H,RO
TX SRAM write pointer address high byte (21H)
7:0
TWPAL
00H.RO
TX SRAM write pointer address low byte (20H)
10.21 TX SRAM Read Pointer Address Register (22H~23H)
Bit
Name
Default
Description
7:0
TRPAH
00H,RO
TX SRAM read pointer address high byte (23H)
7:0
TRPAL
00H.RO
TX SRAM read pointer address low byte (22H)
10.22 RX SRAM Write Pointer Address Register (24H~25H)
Bit
Name
Default
Description
7:0
RWPAH
0CH,RO
RX SRAM write pointer address high byte (25H)
7:0
RWPAL
04H.RO
RX SRAM write pointer address low byte (24H)
10.23 RX SRAM Read Pointer Address Register (26H~27H)
Bit
Name
Default
Description
7:0
RRPAH
0CH,RO
RX SRAM read pointer address high byte (27H)
7:0
RRPAL
00H.RO
RX SRAM read pointer address low byte (26H)
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