ADP3189 datasheet(14/36 Pages) AD

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ADP3189

Rev. 0 | Page 14 of 36

To increase the current in any given phase, enlarge RSW for that

phase (make RSW = 0 for the hottest phase and do not change

during balancing). Increasing RSW to only 500 Ω makes a

substantial increase in phase current. Increase each RSW value

by small amounts to achieve balance, starting with the coolest

phase first.

VOLTAGE CONTROL MODE

A high gain-bandwidth voltage mode error amplifier is used for

the voltage-mode control loop. The control input voltage to the

positive input is set via the VID logic according to the voltages

listed in Table 4.

This voltage is also offset by the droop voltage for active

positioning of the output voltage as a function of current,

commonly known as active voltage positioning. The output

of the amplifier is the COMP pin, which sets the termination

voltage for the internal PWM ramps.

The negative input (FB) is tied to the output sense location with

a resistor RB and is used for sensing and controlling the output

voltage at this point. A current source from the FB pin flowing

through RB is used for setting the no-load offset voltage from

the VID voltage. The no-load voltage is negative with respect to

the VID DAC. The main loop compensation is incorporated

into the feedback network between FB and COMP.

DELAY TIMER

The delay times for the start-up timing sequence are set with

a capacitor from the DELAY pin to ground. In UVLO, or when

EN is logic low, the DELAY pin is held at ground. After the

UVLO and EN signals are asserted, the first delay time (TD1 in

Figure 8) is initiated. A 15 μA current flows out of the DELAY

pin to charge CDLY. A comparator monitors the DELAY voltage

with a threshold of 1.7 V. The delay time is therefore set by the

15 μA charging a capacitor from 0 V to 1.7 V. This DELAY pin

is used for multiple delay timings (TD1, TD3, and TD5) during

the start-up sequence. Also, DELAY is used for timing the

current limit latch off, as explained in the Current Limit, Short

Circuit, and Latch-Off Protection section.

SOFT START

The Soft Start times for the output voltage are set with a capacitor

from the SS pin to ground. After TD1 and the phase detection

cycle have been completed, the SS time (TD2 in Figure 8) starts.

The SS pin is disconnected from GND, and the capacitor is

charged up to the 1.1 V boot voltage by the SS amplifier, which

has a limited output current of 15 μA. The voltage at the FB pin

follows the ramping voltage on the SS pin, limiting the inrush

current during start-up. The soft start time depends on the

value of the boot voltage and CSS.

Once the SS voltage is within 100 mV of the boot voltage, the

boot voltage delay time (TD3) is started. The end of the boot

voltage delay time signals the beginning of the second soft start

time (TD4). The SS voltage now changes from the boot voltage

to the programmed VID DAC voltage (either higher or lower)

using the SS amplifier with the limited output current of 15 μA.

The voltage of the FB pin follows the ramping voltage of the SS

pin, limiting the inrush current during the transition from the

boot voltage to the final DAC voltage. The second soft start

time depends on the boot voltage, the programmed VID DAC

voltage, and CSS.

If either EN is taken low or VCC drops below UVLO, DELAY

and SS are reset to ground to be ready for another soft start

cycle. Figure 9 shows typical start-up waveforms for the

ADP3189.

CH1 1.0V

CH2 1.0V

CH3 1.0V

CH4 10.0V

M2.00ms

A CH1

500V

T 22.0%

Figure 9. Typical Start-up Waveforms

Channel 1: CSREF, Channel 2: DELAY,

Channel 3: SS, Channel 4: Phase 1 Switch Node

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