ADP3189 datasheet(29/36 Pages) AD

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ADP3189

Rev. 0 | Page 29 of 36

CURRENT LIMIT SETPOINT

FEEDBACK LOOP COMPENSATION DESIGN

To select the current limit setpoint, first find the resistor value

for RLIM. The current limit threshold for the ADP3189 is set

with a 1.7 V source (VLIM) across RLIM with a gain of 10 mV/μA

(ALIM). RLIM can be found using

CSA

LIM

(27)

Optimized compensation of the ADP3189 allows the best

possible response of the regulator’s output to a load change.

The basis for determining the optimum compensation is to

make the regulator and output decoupling appear as an output

impedance that is entirely resistive over the widest possible

frequency range, including dc, and equal to the droop resis-

tance (RO). With the resistive output impedance, the output

voltage droops in proportion to the load current at any load

current slew rate. This ensures the optimal positioning and

allows the minimization of the output decoupling.

For values of RLIM greater than 500 kΩ, the current limit may be

lower than expected, so some adjustment of RLIM is needed. Here,

ILIM is the peak average current limit for the supply output. In this

example, choosing a peak current limit of 170 A for ILIM, results

in RLIM = 100 kΩ, and 100 kΩ is chosen as the nearest 1% value.

The per-phase initial duty cycle limit and peak current during a

load step are determined by

()

BIAS

MAX

COMP

MAX

−

(28)

With the multimode feedback structure of the ADP3189, the

feedback compensation must be set to make the converter’s

output impedance, working in parallel with the output decoup-

ling, to meet this goal. Several poles and zeros created by the

output inductor and decoupling capacitors (output filter) need

to be compensated for.

(

)

VID

MAX

PHMAX

−

≅

(29)

A type-three compensator on the voltage feedback is adequate

for proper compensation of the output filter. Equation 31 to

Equation 35 are intended to yield an optimal starting point for

the design; some adjustments may be necessary to account for

PCB and component parasitic effects (see the Tuning the

ADP3189 section).

For the ADP3189, the maximum COMP voltage (VCOMP(MAX)) is

4.0 V and the COMP pin bias voltage (VBIAS) is 1.1 V. In this

example, the maximum duty cycle is 0.61 and the peak current

is 62 A.

First, compute the time constants for all the poles and zeros in

the system, using Equation 31 to Equation 35 on the next page.

The limit of the peak per-phase current described earlier during

the secondary current limit is determined by

()

MAX

BIAS

CLAMPED

COMP

PHLIM

−

≅

(30)

For the ADP3189, the current balancing amplifier gain (AD) is 5,

and the clamped COMP pin voltage is 2 V. Using an RDS(MAX) of

2.8 mΩ (low-side on resistance at 150°C) results in a per-phase

peak current limit of 64 A. This current level can be reached

only with an absolute short at the output, and the current limit

latch-off function shuts down the regulator before overheating

can occur.

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