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ADP3189

Rev. 0 | Page 27 of 36

Using ten 560 μF Al-Poly capacitors with a typical ESR of 6 mΩ

each yields CX = 5.6 mF with an RX = 0.6 mΩ.

One last check should be made to ensure that the ESL of the

bulk capacitors (LX) is low enough to limit the high frequency

ringing during a load change.

This is tested using

()

mΩ

μF

180

≤

(19)

where Q2 is limited to 4/3 to ensure a critically damped system.

In this example, LX is approximately 240 pH for the ten

A1-Polys capacitors, which satisfies this limitation. If the LX

of the chosen bulk capacitor bank is too large, the number of

ceramic capacitors may need to be increased, or lower ESL bulks

used if there is excessive undershoot during a load transient.

For this multimode control technique, all ceramic designs can

be used providing the conditions of Equation 16, Equation 17,

Equation 18, and Equation 19 are satisfied.

POWER MOSFETS

For this example, the N-channel power MOSFETs have been

selected for one high-side switch and two low-side switches per

phase. The main selection parameters for the power MOSFETs

are VGS(TH), QG, CISS, CRSS, and RDS(ON). The minimum gate drive

voltage (the supply voltage to the ADP3120) dictates whether

standard threshold or logic-level threshold MOSFETs must be

used. With VGATE ~10 V, logic-level threshold MOSFETs

(VGS(TH) < 2.5 V) are recommended.

The maximum output current (IO) determines the RDS(ON)

requirement for the low-side (synchronous) MOSFETs. With

the ADP3189, currents are balanced between phases, thus the

current in each low-side MOSFET is the output current divided

by the total number of MOSFETs (nSF). With conduction losses

being dominant, the following expression shows the total power

being dissipated in each synchronous MOSFET in terms of the

ripple current per phase (IR) and average total output current (IO):

()

⎥

⎦

⎤

⎢

⎣

⎡

⎟⎟

⎠

⎞

⎜⎜

⎝

⎛

⎟⎟

⎠

⎞

⎜⎜

⎝

⎛

−

(20)

Knowing the maximum output current being designed for and

the maximum allowed power dissipation, the user can find the

required RDS(ON) for the MOSFET. For D-PAK MOSFETs up to

an ambient temperature of 50°C, a safe limit for PSF is 1 W to

1.5 W at 120°C junction temperature. Thus, for this example

(119 A maximum), RDS(SF) (per MOSFET) < 7.5 mΩ. This RDS(SF)

is also at a junction temperature of about 120°C, so be certain to

account for this when making this selection. This example uses

two lower-side MOSFETs at 4.8 mΩ, each at 120°C.

Another important factor for the synchronous MOSFET is the

input capacitance and feedback capacitance. The ratio of the

feedback to input needs to be small (less than 10% is recom-

mended) to prevent accidental turn-on of the synchronous

MOSFETs when the switch node goes high.

Also, the time to switch the synchronous MOSFETs off should

not exceed the nonoverlap dead time of the MOSFET driver

(40 ns typical for the ADP3120). The output impedance of the

driver is approximately 2 Ω, and the typical MOSFET input gate

resistances are about 1 Ω to 2 Ω, so a total gate capacitance of

less than 6000 pF should be adhered to. Since there are two

MOSFETs in parallel, the input capacitance for each synchronous

MOSFET should be limited to 3000 pF.

The high-side (main) MOSFET has to be able to handle two

main power dissipation components: conduction and switching

losses. The switching loss is related to the amount of time it

takes for the main MOSFET to turn on and off, and to the

current and voltage that are being switched. Basing the switching

speed on the rise and fall time of the gate driver impedance and

MOSFET input capacitance, the following expression provides

an approximate value for the switching loss per main MOSFET,

where nMF is the total number of main MOSFETs:

()

ISS

= 2

(21)

where RG is the total gate resistance (2 Ω for the ADP3120 and

about 1 Ω for typical high speed switching MOSFETs, making

RG = 3 Ω), and CISS is the input capacitance of the main MOSFET.

Adding more main MOSFETs (nMF) does not help the switching

loss per MOSFET, since the additional gate capacitance slows

switching. Use lower gate capacitance devices to reduce

switching loss.

The conduction loss of the main MOSFET is given by the

following, where RDS(MF) is the on resistance of the MOSFET:

()

⎥

⎦

⎤

⎢

⎣

⎡

⎟⎟

⎠

⎞

⎜⎜

⎝

⎛ ×

⎟⎟

⎠

⎞

⎜⎜

⎝

⎛

(22)

Typically, for main MOSFETs, the highest speed (low CISS)

device is preferred, but these usually have higher on resistance.

Select a device that meets the total power dissipation (about

1.5 W for a single D-PAK) when combining the switching and

conduction losses.

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