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ADP3189

Rev. 0 | Page 16 of 36

The PWRGD circuitry also incorporates an initial turn-on

delay time (TD5), based on the DELAY timer. Prior to the

SS voltage reaching the programmed VID DAC voltage and the

PWRGD masking time finishing, the PWRGD pin is held low.

Once the SS pin is within 100 mV of the programmed DAC

voltage, the capacitor on the DELAY pin begins to charge up.

A comparator monitors the DELAY voltage and enables

PWRGD when the voltage reaches 1.7 V. The PWRGD delay

time is, therefore, set by a current of 15 μA, charging a capacitor

from 0 V to 1.7 V.

OUTPUT CROWBAR

As part of the protection for the load and output components

of the supply, the PWM outputs are driven low, turning on the

low-side MOSFETs, when the output voltage exceeds the upper

crowbar threshold. This crowbar action stops once the output

voltage falls below the release threshold of approximately

375 mV.

Turning on the low-side MOSFETs pulls down the output as

the reverse current builds up in the inductors. If the output

overvoltage is due to a short in the high-side MOSFET, this

action current-limits the input supply or blows its fuse,

protecting the microprocessor from being destroyed.

OUTPUT ENABLE AND UVLO

For the ADP3189 to begin switching, the input supply (VCC)

to the controller must be higher than the UVLO threshold,

and the EN pin must be higher than its 0.85 V threshold. This

initiates a system start up sequence. If either UVLO or EN is

less than their respective thresholds, the ADP3189 is disabled.

This holds the PWM outputs at ground, shorts the DELAY

capacitor to ground, and forces PWRGD and OD signals low.

In the application circuit, the OD pin should be connected to

the OD inputs of the ADP3120 driver. Grounding OD disables

the drivers such that both DRVH and DRVL are grounded. This

feature is important in preventing the discharge of the output

capacitors when the controller is shut off. If the driver outputs

were not disabled, a negative voltage can be generated during

output due to the high current discharge of the output

capacitors through the inductors.

THERMAL MONITORING

The ADP3189 includes a thermal monitoring circuit to detect

when a point on the VR has exceeded two different user-defined

temperatures. The thermal monitoring circuit requires an NTC

thermistor to be placed between TTSENSE and GND. A fixed

current of 120 μA is sourced out of the TTSENSE pin and into

the thermistor. The current source is internally limited to 5 V.

An internal circuit compares the TTSENSE voltage to a 1.11 V

and a 0.81 V threshold, and outputs an open-drain signal at the

VRFAN and VRHOT outputs, respectively. Once the voltage on

the TTSENSE pin goes below its respective threshold, the open

drain outputs assert high to signal the system that an overtem-

perature event has occurred. Since the TTSENSE voltage changes

slowly with respect to time, 55 mV of hysteresis is built into these

comparators. The thermal monitoring circuitry does not depend

on EN and is active when UVLO is above its threshold. When

UVLO is below its threshold, VRFAN and VRHOT are

forced low.

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