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ADP3189 Datasheet(PDF) 26 Page - Analog Devices |
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ADP3189 Datasheet(HTML) 26 Page - Analog Devices |
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26 / 36 page  ADP3189 Rev. 0 | Page 26 of 36 OUTPUT OFFSET The Intel specification requires that at no load the nominal output voltage of the regulator is offset to a value lower than the nominal voltage corresponding to the VID code. The offset is set by a constant current source flowing out of the FB pin (IFB) and flowing through RB. The value of RB can be found using Equation 15: FB ONL VID B I V V R − = Ω k 00 . 1 μA 15 V 285 . 1 V 3 . 1 = − = B R (15) The closest standard 1% resistor value is 1.00 kΩ. COUT SELECTION The required output decoupling for the regulator is typically recommended by Intel for various processors and platforms. Use some simple design guidelines to determine the require- ments. These guidelines are based on having both bulk capacitors and ceramic capacitors in the system. First, select the total amount of ceramic capacitance. This is based on the number and type of capacitor to be used. The best location for ceramic capacitors is inside the socket, with 12 to 18 of size, 1206 being the physical limit. Other capacitors can be placed along the outer edge of the socket as well. To aid in determining the minimum amount of ceramic capacitance required, start with a worst-case load step occur- ring right after a switching cycle has stopped. The ceramic capacitance then delivers the charge to the load while the load is ramping up and until the VR has responded with the next switching cycle. The following equation gives the designer a rough approximation for determining the minimum ceramic capacitance needed. Due to the complexity of the PCB parasitics and bulk capacitors, the actual amount of ceramic capacitance required may vary. () ⎥ ⎦ ⎤ ⎢ ⎣ ⎡ − ⎟ ⎠ ⎞ ⎜ ⎝ ⎛ − × × ≥ R O SW O MIN Z S I D n f R C 2 Δ 1 1 1 (16) The typical ceramic capacitors used are made up of multiple 10 μF or 22 μF capacitors. For this example, Equation 16 yields 180.8 μF, so eighteen 10 uF ceramics will suffice. Next, there is an upper limit imposed on the total amount of bulk capacitance (CX) when the user considers the VID on-the- fly voltage stepping of the output (voltage step V A lower limit is based on meeting the capacitance for load release for a given maximum load step ΔIO and a maximum allowable overshoot. The total amount of load release voltage is given as Δ VO = ΔIO × RO + ΔVrl, where ΔVrl is the maximum allowable overshoot voltage. () ⎟ ⎟ ⎟ ⎟ ⎟ ⎠ ⎞ ⎜ ⎜ ⎜ ⎜ ⎜ ⎝ ⎛ − × ⎟⎟ ⎠ ⎞ ⎜⎜ ⎝ ⎛ Δ Δ + × × ≥ z VID O rl O O MIN x C V I V R n I L C Δ (17) () ≤ MAX x C (18) z O V VID v VID V 2 O 2 C L nKR V V t V V R nK L − ⎟ ⎟ ⎟ ⎠ ⎞ ⎜ ⎜ ⎜ ⎝ ⎛ − ⎟⎟ ⎠ ⎞ ⎜⎜ ⎝ ⎛ × + × × 1 1 2 ⎟⎟ ⎠ ⎞ ⎜⎜ ⎝ ⎛ − = V ERR V V 1n K where To meet the conditions of these expressions and transient response, the ESR of the bulk capacitor bank (RX) should be less than two times the droop resistance (RO). If the CX(MIN) is larger than CX(MAX), the system cannot meet the VID on-the-fly speci- fication and can require the use of a smaller inductor or more phases (and may have to increase the switching frequency to keep the output ripple the same). This example uses eighteen 10 μF 1206 MLC capacitors (CZ = 180 F). The VID on-the-fly step change is 450 mV in 230 μs with a setting error of 2.5 mV. The maximum allowable load release overshoot for this example is 50 mV, therefore solving for the bulk capacitance yields () mF 92 . 3 μF 180 V 3 . 1 A 100 mV 50 mΩ 0 . 1 4 A 100 nH 320 = ⎟⎟ ⎟ ⎟ ⎟ ⎟ ⎠ ⎞ ⎜⎜ ⎜ ⎜ ⎜ ⎜ ⎝ ⎛ − × ⎟ ⎟ ⎠ ⎞ ⎜ ⎜ ⎝ ⎛ + × × ≤ MIN x C () () × × × × × ≤ V 3 . 1 Ω m 0 . 1 2 . 5 4 mV 450 nH 320 2 2 MAX x C mF 0 43 μF 180 1 nH 320 mV 450 Ω m 0 1 2 5 4 3 1 μs 230 1 2 . . . V . = − ⎟ ⎟ ⎟ ⎠ ⎞ ⎜ ⎜ ⎜ ⎝ ⎛ − ⎟ ⎟ ⎠ ⎞ ⎜ ⎜ ⎝ ⎛ × × × × × + V in time tV with error of VERR). where K = 5.2 |
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