DP83261AVF datasheet(23/132 Pages) NSC

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60 Control Information

The Control Information includes Operation Event Status

and Parameter Registers that are used to manage and op-

erate the Ring Engine A processor on the external Control

Bus gains access to read and write these parameters via

the Control Interface

The Control Information Address Space is divided into 4

groups as shown in Table 6-1 An information summary is

given for each group (see Tables 6-2 through 6-5) followed

by a detailed description of all registers

61 CONVENTIONS

When referring to multi-byte fields byte 0 is always the most

significant byte When referring to bits within a byte bit (7) is

the most significant bit and bit (0) is the least significant bit

When referring to the contents of a byte the most signficant

bit is always referred to first

When referring to a bit within a byte the notation

namebit

name is used For example ModeRUN

references the RUN bit in the Mode Register

62 ACCESS RULES

All parameters are accessible in Diagnose Mode Reserved

address space is not accessible in any mode Certain Status

and Parameter Registers are not accessible while in Run

mode

All Control Interface accesses are checked against the cur-

rent operational mode to determine if the register is current-

ly accessible If not currently accessible the Control Bus

Interface access is rejected (and reported in an Event Reg-

ister) This means that all Control Bus Interface accesses

complete in a deterministic amount of time

The Exceptional Status Register can be checked to verify

that the operation terminated normally

TABLE 6-1 Control Information Address Space

Address Range

Description

Read Conditions

Write Conditions

00 – 07

Operation Registers

Always (Note 2)

08 – 2F

Event Registers

Always (Note 2)

Always (Cond) (Note 2)

30 – 3F

Reserved

40 – 7F

MAC Parameters

Stop Mode

(Notes 1 3)

80 – BF

CountersTimers

Always

Stop Mode

(Note 1)

C0 – FF

Reserved

Note 1

An attempt to access a currently inaccessible location because of the current mode or because it is in a reserved address space will cause a command

error (bit CCE of the Exception Status Register is set to One)

Note 2

Read and write accesses to reserved location within the Operation and Event Address ranges cause a command error (bit CCE of the Exception Status

Note 3

The MAC Parameter RAM is also accessible when conditions a b and c are true Otherwise accesses will cause a command error (ESRCEE set to One)

and the access will not be performed

a The MAC Transmitter is in states T0 T1 or T3

b Bits ITC and IRR of the Option Register are set to One

c Bits CLM and BCN of the Function Register are not set to One

TABLE 6-2 Operation Registers

Addr

Name

Read

Write

Mode

DIAG

ILB

RES

PIP

MRP

CBP

RUN

Always

Option

ITC

EMIND

IFCS

IRPT

IRR

ITR

ELA

ESA

Always

Function

RES

CLM

BCN

MCRST

RES

MARST

Always

3 – 6

Reserved

RES

Revision

REV(7 – 0)

Always

Note

Attempts to access reserved locations will result in Command Rejects (ESRCCE set to ONE)

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