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DP83261AVF Datasheet(PDF) 34 Page - National Semiconductor (TI) |
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DP83261AVF Datasheet(HTML) 34 Page - National Semiconductor (TI) |
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34 / 132 page  60 Control Information (Continued) Current Receiver Status Register (CRS0) The Current Receiver Status Register (CRS0) records the status of the Receiver state machine It is continuously updated It remains stable when accessed When in Diagnose Mode this register is frozen on an internal error until the internal error event is cleared by resetting the RSMERR bit in the Internal Event Latch Register ACCESS RULES Address Read Write 0Ch Always Data Ignored REGISTER BITS D7 D6 D5 D4 D3 D2 D1 D0 RFLG RS2 RS1 RS0 RES RTS2 RTS1 RTS0 Bit Symbol Description D0 – 2 RTS(0 – 2) Receive Timing State RTS(0 – 2) represent the current state of the Receiver Timing state machine The encoding is shown below RTS2 RTS1 RTS0 Receive Timing State 0 0 1 Await SD 0 0 1 Check FC 0 1 0 Check SA 0 1 1 Check DA 1 0 0 Check INFO 1 0 1 Check MAC 1 1 x Reserved D3 RES Reserved D4–6 RS(0–2) Receive State RS(0 – 2) represent the current state of the Receive state machine that implements the ANSI standard MAC Receive Functions The encoding is shown below RS2 RS1 RS0 Receive State 0 0 0 Listen 0 0 1 Await SD 01 0 RC FR CTRL (Receive FC) 01 1 RC FR BODY (Rec FR Body) 10 0 RC FR STATUS (A C Ind) 1 0 1 CHECK TOKEN (Check Token) 11 0 RC FR STATUS (Optional Ind) 1 1 1 Reserved D7 RFLG R Flag Current value of the Restricted Flag When not holding the token indicates the type of the last valid token received When holding the token indicates the type of token that will be issued at the end of the current service opportunity 0 Non-restricted 1 Restricted 34 |
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