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DP83261AVF Datasheet(PDF) 25 Page - National Semiconductor (TI) |
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DP83261AVF Datasheet(HTML) 25 Page - National Semiconductor (TI) |
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25 / 132 page ![]() 60 Control Information (Continued) TABLE 6-4 MAC Parameter RAM Address Name Register Contents 40 MLA0 MLA(47 – 40) 41 MLA1 MLA(39 – 32) 42 MLA2 MLA(31 – 24) 43 MLA3 MLA(23-16) 44 MLA4 MLA(15 – 8) 45 MLA5 MLA(7 – 0) 46 MSA0 MSA(15 – 8) 47 MSA1 MSA(7 – 0) 48 GLA0 GLA(47 – 40) 49 GLA1 GLA(39 – 32) 4A GLA2 GLA(31 – 24) 4B GLA3 GLA(23 – 16) 4C GLA4 GLA(15 – 8) 4D Reserved 4E GSA0 GSA(15 – 8) 4F Reserved 50 TREQ0 TREQ(31 – 24) 51 TREQ1 TREQ(23 – 16) 52 TREQ2 TREQ(15 – 8) 53 TREQ3 TREQ(7 – 0) 54 TBT0 TBT(31 – 24) 55 TBT1 TBT(23 – 16) 56 TBT2 TBT(15 – 8) 57 TBT3 TBT(7 – 0) 58 FGM0 FGM(7 – 0) 59 FGM1 FGM(F – 8) 5A – 5F RES Reserved Note The MAC Parameter RAM is accessible in Stop mode and in RUN mode while the MAC Transmitter is in the states T0T1 or T3 OptionITC and OptionIRR are set and FunctionBCN and FunctionCLM are not set Other- wise a command reject is given (ESRCCE) and the Parameter RAM will not be read or written TABLE 6-4 MAC Parameter RAM (Continued) Address Name Register Contents 60 PGM10 PGM(87 – 80) 61 PGM11 PGM(8F – 88) 62 PGM12 PGM(97 – 90) 63 PGM13 PGM(9F – 98) 64 PGM14 PGM(A7 – A0) 65 PGM15 PGM(AF – A8) 66 PGM16 PGM(B7 – B0) 67 PGM17 PGM(BF – B8) 68 PGM18 PGM(C7 – C0) 69 PGM19 PGM(CF – C8) 6A PGM1A PGM(D7 – D0) 6B PGM1B PGM(DF – D8) 6C PGM1C PGM(E7 – E0) 6D PGM1D PGM(EF – E8) 6E PGM1E PGM(F7 – F0) 6F PGM1F PGM(FF – F8) 70 PGM0 PGM(7 – 0) 71 PGM1 PGM(F – 8) 72 PGM2 PGM(17 – 10) 73 PGM3 PGM(1F – 18) 74 PGM4 PGM(27 – 20) 75 PGM5 PGM(2F – 28) 76 PGM6 PGM(37 – 30) 77 PGM7 PGM(3F – 38) 78 PGM8 PGM(47 – 40) 79 PGM9 PGM(4F – 48) 7A PGMA PGM(57 – 50) 7B PGMB PGM(5F – 58) 7C PGMC PGM(67 – 60) 7D PGMD PGM(6F – 68) 7E PGME PGM(77 – 70) 7F PGMF PGM(7F – 78) 25 |
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