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DP83261AVF Datasheet(PDF) 61 Page - National Semiconductor (TI) |
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DP83261AVF Datasheet(HTML) 61 Page - National Semiconductor (TI) |
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61 / 132 page  60 Control Information (Continued) 67 EVENT COUNTERS The Event Counters are used to gain access to the internal 20-bit counters used to gather statistics The following event counters are included Frame Received Counter (FRCT1–3) Error Isolated Counter (EICT1–3) Lost Frame Counter (LFCT1–3) Frame Copied Counter (FCCT1–3) Frame Not Copied Counter (FNCT1–3) Frame Transmitted Counter (FTCT1–3) Token Received Counter (TKCT1–3) Ring Latency Counter (RLCT1–3) Late Count Counter (LTCT) 671 Processing Procedures The counters are 20-bit wrap-around counters except for the Late Count Counter which is a 4-bit sticky counter (see Figure 6-2 ) Since the Control Bus Interface is an 8-bit interface and the counters are 20-bits wide a register holding scheme is implement- ed In order to provide a consistent snapshot of a counter while the least significant byte is read the upper 12 bits are loaded into a holding which can then be read The least significant byte must be read first The Counters are always readable and are writable in Stop Mode The Counters are not reset as a result of a Master Reset This may be done by either reading the Counters out and keeping track relative to the initial value read or by writing a value (Zero) to all of the Counters in Stop Mode The Counters may be written in any order Interrupts may be requested when the counters increment (except for Ring Latency Counter) or wrap-around (except for Ring Latency Counter and Late Count Counter) TLF10387 – 10 FIGURE 6-2 Event Counters 61 |
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