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DP83261AVF Datasheet(PDF) 41 Page - National Semiconductor (TI) |
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DP83261AVF Datasheet(HTML) 41 Page - National Semiconductor (TI) |
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41 / 132 page  60 Control Information (Continued) Token and Timer Event Mask Register 0 (TEMR0) The Token and Timer Event Mask Register 0 (TEMR0) is used to mask bits in Register TELR0 If a bit in Register TEMR0 is set to One the corresponding bit in Register TELR will be applied to the Interrupt Condition Register which can then be used to generate an interrupt All bits in this register are set to Zero upon reset ACCESS RULES Address Read Write 15h Always Always REGISTER BITS D7 D6 D5 D4 D3 D2 D1 D0 RLVD TKPASS TKCAPT CBERR DUPTOK TRTEXP TVXEXP ENTRMD Bit Symbol Description D0 ENTRMD Enter Restricted Mode Mask This bit is used to mask TELR0ENTRMD D1 TVXEXP TVX Expired Mask This bit is used to mask TELR0TVXEXP D2 TRTEXP TRT Expired and Set Late Flag Mask This bit is used to mask TELR0TRTEXP D3 DUPTOK Duplicated Token Received Mask This bit is used to mask TELR0DUPTOK D4 CBERR ClaimBeacon Error Mask This bit is used to mask TELR0CBERR D5 TKCAPT Token Captured Mask This bit is used to mask TELR0TKCAPT D6 TKPASS Token Passed Mask This bit is used to mask TELR0TKPASS D7 RLVD Ring Latency Valid Mask This bit is used to mask TELR0RLVD 41 |
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