DP83261AVF datasheet(26/132 Pages) NSC

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60 Control Information (Continued)

TABLE 6-5 MAC Counters and Timer Thresholds

Address

Name

Contents

80 – 86

Reserved

THSH1

Null(7 – 4)

THSH1(3 – 0)

88 – 92

Reserved

TMAX

Null(7 – 4)

TMAX(3 – 0)

94 – 96

Reserved

TVX

Null(7 – 4)

TVX(3 – 0)

TNEG0

TNEG(31 – 24)

TNEG1

TNEG(23 – 16)

TNEG2

TNEG(15 – 8)

TNEG3

TNEG(7 – 0)

9C – 9E

Reserved

LTCT

Null(7 – 4)

LTCT(3 – 0)

FRCT0

Zero(31 – 24)

FRCT1

Null(7 – 4)

FRCT(19 – 16)

FRCT2

FRCT(15 – 8)

FRCT3

FRCT(7 – 0)

EICT0

Zero(31 – 24)

EICT1

Null(7 – 4)

EICT(19 – 16)

EICT2

EICT(15 – 8)

EICT3

EICT(7 – 0)

LFCT0

Zero(31 – 24)

LFCT1

Null(7 – 4)

LFCT(19 – 16)

LFCT2

LFCT(15 – 8)

LFCT3

LFCT(7 – 0)

FCCT0

Zero(31 – 24)

FCCT1

Null(7 – 4)

FCCT(19 – 16)

FCCT2

FCCT(15 – 8)

FCCT3

FCCT(7 – 0)

TABLE 6-5 MAC Counters and Timer Thresholds

(Continued)

Address

Name

Contents

FNCT0

Zero(31 – 24)

FNCT1

Null(7 – 4)

FNCT(19 – 16)

FNCT2

FNCT(15 – 8)

FNCT3

FNCT(7 – 0)

FTCT0

Zero(31 – 24)

FTCT1

Null(7 – 4)

FTCT(19 – 16)

FTCT2

FTCT(15 – 8)

FTCT3

FTCT(7 – 0)

TKCT0

Zero(31 – 24)

TKCT1

Null(7 – 4)

TKCT(19 – 16)

TKCT2

TKCT(15 – 8)

TKCT3

TKCT(7 – 0)

RLCT0

Zero(31 – 24)

RLCT1

Null(7 – 4)

RLCT(19 – 16)

RLCT2

RLCT(15 – 8)

RLCT3

RLCT(7 – 0)

Note

The MAC event counters and timer thresholds are always readable

and are writable in Stop mode

Note

Null(7–4) indicates that these bits are forced to zero on reads and are

ignored on writes

Note

The value obtained on reads from reserved locations is not specified

The Event Counters are 20-bit counters and are read

through three control accesses In order to guarantee a

consistent snapshot whenever byte 3 of an event counter is

read byte 1 and byte 2 of the counters are loaded into a

holding register Byte 1 and byte 2 may then be read from

the holding register A single holding register is shared by all

of the counters but (for convenience) is accessible at sever-

al places within the address space Consistent readings

across counters can be accomplished using the Counter

Increment Latch Register (CILR)

The Event Counters are not reset as a result of a Master

Reset This may be done by either reading the counters out

and keeping track relative to the initial value read or by

writing a value to all of the counters in stop mode The

counters may be written in any order With some excep-

tions interrupts are available when the counters increment

or wraparound

63 OPERATION REGISTERS

The Operation Registers are used to control the operation

of the BMAC device The Operation Registers include the

following registers

Mode Register (Mode)

Option Register (Option)

Function Register (Function)

Revision Register (REV)

DP83261AVF Datasheet(PDF) 26 Page - National Semiconductor (TI)

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