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DP83261AVF Datasheet(PDF) 45 Page - National Semiconductor (TI) |
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DP83261AVF Datasheet(HTML) 45 Page - National Semiconductor (TI) |
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45 / 132 page ![]() 60 Control Information (Continued) Counter Overflow Mask Register (COMR) The Counter Overflow Mask Register (COMR) is used to mask bits from the Counter Overflow Latch Register (COLR) If a bit in Register COMR is set to One the corresponding bit in Register COLR will be applied to the Interrupt Condition Register which can then be used to generate an interrupt All bits in this register are set to Zero upon reset ACCESS RULES Address Read Write 1Dh Always Always REGISTER BITS D7 D6 D5 D4 D3 D2 D1 D0 RES TKRCVD FRTRX FRNCOP FRCOP FRLST FREI FRRCV Bit Symbol Description D0 FRRCV Frame Received Counter Overflow Mask This bit is used to mask COLRFRRCV D1 FREI Error Isolated Counter Overflow Mask This bit is used to mask COLRFREI D2 FRLST Lost Frame Counter Overflow Mask This bit is used to mask COLRFRLST D3 FRCOP Frame Copied Counter Overflow Mask This bit is used to mask COLRFRCOP D4 FRNCOP Frame Not Copied Counter Overflow Mask This bit is used to mask COLRFRNCOP D5 FRTRX Frame Transmitted Counter Overflow Mask This bit is used to mask COLRFRTRX D6 TKRCVD Token Received Counter Overflow Mask This bit is used to mask COLRTKRCVD D7 RES Reserved 45 |
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