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DP83261AVF Datasheet(PDF) 37 Page - National Semiconductor (TI) |
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DP83261AVF Datasheet(HTML) 37 Page - National Semiconductor (TI) |
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37 / 132 page  60 Control Information (Continued) Ring Event Mask Register 0 (REMR0) The Ring Event Mask Register 0 (REMR0) is used to mask bits in Register RELR0 If a bit in Register REMR0 is set to One the corresponding bit in Register RELR0 will be applied to the Interrupt Condition Register which can then be used to generate an interrupt ACCESS RULES Address Read Write 11h Always Always REGISTER BITS D7 D6 D5 D4 D3 D2 D1 D0 RES DUPADD PINV OTRMAC CLMR BCNR RNOP ROP Bit Symbol Description D0 ROP Ring Operational Mask This bit is used to mask RELR0ROP D1 RNOP Ring Non-Operational Mask This bit is used to mask RELR0RNOP D2 BCNR Beacon Frame Mask This bit is used to mask RELR0BCNR D3 CLMR Claim Frame Mask This bit is used to mask RELR0CLMR D4 OTRMAC Other MAC Frame Mask This bit is used to mask RELR0OTRMAC D5 PINV PHY Invalid Mask This bit is used to mask RELR0PINV D6 DUPADD Duplicate Address Mask This bit is used to mask RELR0DUPADD D7 RES Reserved 37 |
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