W5500 datasheet(9/66 Pages) WIZNET

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W5500 Datasheet Version1.0.9

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This pin must be connected to a 10nF capacitor.

This is the output voltage of the internal regulator.

RSVD

Pull-down

It must be tied to GND.

SPDLED

Speed LED

This shows the Speed status of the connected link.

Low: 100Mbps

High: 10Mbps

LINKLED

Link LED

This shows the Link status.

Low: Link is established

High: Link is not established

DUPLED

Duplex LED

This shows the Duplex status for the connected link.

Low: Full-duplex mode

High: Half-duplex mode

ACTLED

Active LED

This shows that there is Carrier sense (CRS) from the

active Physical Medium Sub-layer (PMD) during TX or RX

activity.

Low: Carrier sense from the active PMD

High: No carrier sense

VDD

PWR

Digital 3.3V Power

GND

Digital Ground

XI/CLKIN

Crystal input / External Clock input

External 25MHz Crystal Input.

This pin can also be connected to single-ended TTL

oscillator (CLKIN). 3.3V clock should be applied for the

External Clock input. If this method is implemented, XO

should be left unconnected.

Refer to the ‘Crystal reference schematic’ (Figure.3) for

details.

Crystal output

External 25MHz Crystal Output

Note: Float this pin if using an external clock being

driven through XI/CLKIN

SCSn

Pull-up

Chip Select for SPI bus

This pin can be asserted low to select W5500 in SPI

interface.

Low: selected

W5500 Datasheet(PDF) 9 Page - WIZnet Co., Ltd

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