W5500 datasheet(14/66 Pages) WIZNET

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W5500 Datasheet Version1.0.9

2.2

SPI Frame

W5500 SPI Frame consists of 16bits Offset Address in Address Phase, 8bits Control

Phase and N bytes Data Phase as shown in Figure 7.

The 8bits Control Phase is reconfigured with Block Select bits (BSB[4:0]), Read/Write

Access Mode bit (RWB) and SPI Operation Mode (OM[1:0]).

Block Select bits select the block to which the Offset Address belongs.

Figure 7. SPI Frame Format

W5500 supports Sequential Data Read/Write. It processes the data from the base

(the Offset Address which is set for 2/4/N byte Sequential data processing) and the

next data by increasing the Offset Address (auto increment addressing) by 1.

2.2.1 Address Phase

This Address Phase specifies the 16 bits Offset Address for the W5500 Registers and

TX/RX Buffer Blocks.

The 16-bit Offset Address value is transferred from MSB to LSB sequentially.

The SPI frame with 2/4/N byte data phase supports the Sequential Data Read/Write in

which Offset address automatically increases by 1 every 1 byte data.

16btis Offset Address

Data 1

Bit 15

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

Control Byte

N+2

Data N

7 6 5 4 3 2 1 0

. . .

Address Phase

Control Phase

Data Phase

N >= 1

MSB first

14 13 12 11 10 9 8

Block

Select Bits

Mode

W5500 Datasheet(PDF) 14 Page - WIZnet Co., Ltd