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W5500 Datasheet(PDF) 27 Page - WIZnet Co., Ltd |
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W5500 Datasheet(HTML) 27 Page - WIZnet Co., Ltd |
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27 / 66 page  W5500 Datasheet Version1.0.9 27 / 66 Register and Memory Organization W5500 has one Common Register Block, eight Socket Register Blocks, and TX/RX Buffer Blocks allocated to each Socket. Each block is selected by the BSB[4:0](Block Select Bit) of SPI Frame. Figure 20 shows the selected block by the BSB[4:0] and the available offset address range of Socket TX/RX Buffer Blocks. Each Socket’s TX Buffer Block exists in one 16KB TX memory physically and is initially allocated with 2KB. Also, Each Socket’s RX Buffer Block exists in one 16KB RX Memory physically and is initially allocated with 2KB. Regardless of the allocated size of each Socket TX/RX Buffer, it can be accessible within the 16 bits offset address range (From 0x0000 to 0xFFFF). Refer to ‘Chapter 3.3’ for more information about 16KB TX/RX Memory organization and access method. |
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