W5500 datasheet(18/66 Pages) WIZNET

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W5500 Datasheet Version1.0.9

2.3.1

Write Access in VDM

Figure 8. Write SPI Frame in VDM mode

Figure 8 shows the SPI Frame when the external host accesses W5500 for

writing.

In VDM mode, the RWB signal is ‘1’ (Write), OM[1:0] is ‘00’ in SPI Frame Control

Phase. At this time the External Host assert (High-to-Low) SCSn signal before

transmitting SPI Frame. Then the Host transmits SPI Frame’s all bits to W5500

through MOSI signal. All bits are synchronized with the falling edge of the SCLK.

After finishing the SPI Frame transmit, the Host deasserts SCSn signal (Low-to-

High).

When SCSn is Low and the Data Phase continues, the Sequential Data Write can be

supported.

RWB

SCSn

MOSI

SCLK

12 13 14

16 bits Offset Address

BSB[4:0]

17 18

20 21 22 23

25 26

27 28

29 30 31

8-bit Data 1

MODE0

MODE3

MOSI

MISO

SCSn

SCLK

33 34

35 36 37 37

8N + 16

8N + 24

8-bit Data 2

...

8-bit Data N

...

OM[1:0]

MISO

W 0 0

SCSn shoud be remained low until SPI Frame Transmit done.

SCSn Should be remained low until SPI Frame Transmit done.

SPI Frame Start

SPI Frame End

W5500 Datasheet(PDF) 18 Page - WIZnet Co., Ltd

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