AD2428W datasheet(34/38 Pages) AD

34 / 38 page

Rev. B

Page 34 of 38

January 2020

AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W)

LAYOUT GUIDELINES

The transceivers are highly integrated devices, comprising both

digital sections for audio data, clocks, PLL, and analog A2B

transceiver sections. Use the following design rules to maximize

performance and signal integrity:

• Solder the exposed paddle underneath the transceiver

effectively to the PCB where it is locally connected to the

ground plane. Figure 38 shows transceiver foot print, rec-

ommended solder mask (matching exposed paddle), paste

mask (dividing exposed paddle), and stitching of the

ground plane.

The solder paste under the exposed paddle is split into four

square areas, which minimizes solder wicking through

uncovered thermal vias and prevents sliding or tilting of

the chip during solder reflow. See Soldering Considerations

for Exposed-Pad Packages (EE-352), on the Analog Devices

web site. The exposed paddle is used for a thermal pathway

as well as for electrical connection.

• Place power supply decoupling capacitors as close as possi-

ble to the transceiver chip with the smallest value capacitor

being closest to the pin.

• Route all traces as short as possible, especially the AP/AN

and BP/BN signals.

• Symmetrically route the AP/AN and BP/BN signals to sup-

press EMC. Match routing parasitic capacitance and

inductance.

• Symmetrically shield the AP/AN and BP/BN signals with

ground. Use shields that are at least 0.5 mm wide and

stitched generously with vias to the GND plane. Symmetry

is best achieved with flooded plane areas.

• Do not route switching signals or power supply traces next

to or underneath the AP/AN and BP/BN signals.

• Avoid using trace stubs, especially if they create an asym-

metry on the AP/AN and BP/BN signals. Symmetrically

route into and out of pads rather than branch out.

• Differential impedance trace of the AP/AN and BP/BN sig-

nals should be 100 Ω ± 10% (10 MHz to 100 MHz) on both

sides of the common-mode choke.

• Avoid unnecessary layer transitions for the AP/AN and

BP/BN signals. Match necessary layer transitions for differ-

ential signals.

• Use an impedance of 50 Ω ± 10% to ground on all traces.

• Magnetically separate common-mode chokes from each

other by at least 2 mm.

• Do not route ground or other signals on any layer under-

neath the common-mode chokes. Extend this exclusion at

least 2 mm from between the pads.

• For shielded wires, connect the shield to the local ground.

• Place one side of the inductors in the signal path and bridge

dc signals to the power and ground nets.

• Place termination resistors symmetrically and close to the

common-mode chokes.

• Where possible, flood unused PCB areas with connected

ground planes on all layers.

• Stitch ground planes at least every 5 mm.

• Do not obstruct power supply and ground return paths by

vias.

• Use series resistors (≥33 Ω) near the source of clock and

fast data signals. Also consider footprints for small filter

capacitors for such signal traces.

• Avoid using right angle bends in signal routing. Use

rounded or 45 degree mitered bends instead.

• Use shortest possible signal path on connectors (inner row

of multirow, right angled connectors).

• On multipin connectors, provide at least 3 mm spacing

around differential A2B pin pairs to ensure that A2B signal

pairs are closer to each other than to adjacent signals. The

spacing improves EMC performance.

Use low impedance static signals (ground) symmetrically

on connector pins adjacent to the A2B bus pairs when tight

spacing is required.

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