AD2428W datasheet(22/38 Pages) AD

22 / 38 page

Rev. B

Page 22 of 38

January 2020

AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W)

TEST CONDITIONS

All timing parameters in this data sheet were measured under

the conditions described in this section. Figure 26 shows the

measurement point for ac measurements (except output

enable/disable). The measurement point, VMEAS, is VIOVDD/2 for

VIOVDD (nominal) = 3.3 V.

Output Enable Time Measurement

Output pins are considered enabled when they make a transi-

tion from a high impedance state to the point when they start

driving.

The output enable time, tENA, is the interval from the point when

a reference signal reaches a high or low voltage level to the point

when the output starts driving, as shown on the right side of

Figure 27. If multiple pins are enabled, the measurement value

is that of the first pin to start driving.

Output Disable Time Measurement

Output pins are considered disabled when they stop driving,

enter a high impedance state, and start to decay from the output

high or low voltage. The output disable time, tDIS, is the interval

from when a reference signal reaches a high or low voltage level

to the point when the output stops driving, as shown on the left

side of Figure 27.

Capacitive Loading

Output delays and holds are based on standard capacitive loads

of an average of 6 pF on all pins (see Figure 28). VLOAD is equal

to VIOVDD/2. Figure 29 through Figure 32 show how output rise

time varies with capacitance. The delay and hold specifications

given must be derated by a factor derived from these figures.

The graphs in Figure 29 through Figure 32 cannot be linear out-

side the ranges shown.

Figure 24. GPIO, BCLK, and SYNC Drivers (DS1, 1.8 V IOVDD)

Figure 25. GPIO, BCLK, and SYNC Drivers (DS1, 3.3 V IOVDD)

Figure 26. Voltage Reference Levels for AC Measurements

(Except Output Enable/Disable)

– 10

0.4

0.8

1.2

2.0

VOL

IOVDD = 1.9V @ – 40°C

IOVDD = 1.8V @ 25°C

– 5

IOVDD = 1.7V @ 125°C

– 15

1.6

0.2

0.6

1.4

1.8

SOURCE VOLTAGE (V)

VOH

1.0

2.0

3.0

4.0

–40

VOL

IOVDD = 3.6V @ – 40°C

IOVDD = 3.3V @ 25°C

IOVDD = 3.0V @ 125°C

– 20

– 60

0.5

1.5

2.5

3.5

SOURCE VOLTAGE (V)

VOH

INPUT

OUTPUT

VMEAS

Figure 27. Output Enable/Disable

REFERENCE

SIGNAL

tDIS

OUTPUT STARTS DRIVING

HIGH IMPEDANCE STATE

OUTPUT STOPS DRIVING

tENA

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