AD2428W datasheet(9/38 Pages) AD

9 / 38 page

AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W)

Rev. B

Page 9 of 38

January 2020

ELECTRICAL CHARACTERISTICS

Parameter

Conditions

Min

Typ

Max

Unit

Current

IDVDD

Digital Core Logic Supply Current VDVDD = 1.98 V

9.0

10.5

12.0

IPLLVDD

PLL Supply Current

VPLLVDD = 1.98 V

0.5

1.1

1.5

ITRXVDD

1 Master and last slave only consume half the transceiver current because only one of the two TRX blocks is used.

Transceiver Supply Current

TX enabled, RX disabled, 100% duty cycle

(ITXVDD), VTRXVDD = 3.63 V

9.5

12.0

13.0

TX disabled, RX enabled, 100% duty cycle

(IRXVDD), VTRXVDD = 3.63 V

2.22.8

3.5mA

TX disabled, RX disabled, 0% activity level,

VTRXVDD = 3.63 V

1.01.7

2.5mA

Voltage Regulator (VREG1, VREG2)

VVOUT1

VREG1 Output Voltage

1.80

1.90

1.98

VVOUT2

VREG2 Output Voltage

3.15

3.30

3.45

IVOUT1

2 In a bus powered system, IVOUT has a direct impact on IVSSN and VVIN in other nodes. For more information, see the Power Analysis section.

VREG1 Output Current

40.0

IVOUT2

VREG2 Output Current

50.0

IVEXT1

3, 4

3 Consider the package thermal limits when dissipating current above typical limits. For more information, see the Thermal Characteristics section.

4 Must comply with IVOUT1 and IVOUT2 maximum.

VREG1 External Device Current

IVOUT1 – IPLLVDD – IDVDD – IIOVDD current

available to external device

IVEXT2

3, 4

VREG2 External Device Current

IVOUT2 – ITRXVDD current available to external

device

V

OUT1/VIN

Line Regulation

VVIN = 3.7 V to VIN

0.017

0.055

%/V

V

OUT2/VIN

Line Regulation

VVIN = 3.7 V to VIN

0.013

0.030

0.060

%/V

VVIN = 5.0 V to 8 V

–0.025

+0.005

+0.055

%/V

V

OUT1/IOUT1

Load Regulation

VVIN = 5.0 V, IVOUT1 = 1 mA to 40 mA

0.009

0.017

%/mA

V

OUT2/IOUT2

Load Regulation

VVIN = 5.0 V, IVOUT2 = 1 mA to 50 mA

0.008

0.015

%/mA

IVINQ

Quiescent Current

VVIN =VIN, IVOUT1 = 0 mA, IVOUT2 = 0 mA

530

600

750

μA

IVIN

Operational Current

VVIN = VIN, IVOUT1 = 8 mA, IVOUT2 = 20 mA

CLoad1

VREG1 Load Capacitance

1.0

μF

CLoad2

VREG2 Load Capacitance

2.2

μF

Digital I/O

IIH

Input Leakage, High

VIOVDD = 3.63 V, VIN = 3.63 V

10.0

μA

IIL

Input Leakage, Low

VIOVDD = 3.63 V, VIN = 0 V

10.0

μA

IOZH_I2C

5 Applies to SDA and SCL pins.

Three-State Leakage Current

VIOVDD = 1.9 V, VIN = 3.63 V

10.0

μA

VOH1.9

High Level Output Voltage

VIOVDD = 1.70 V, IOH = 1 mA

1.35

VOH3.3

High Level Output Voltage

VIOVDD = 3.00 V, IOH = 1 mA

2.40

VOL

6 Applies to BCLK, SYNC, DTX0/IO3, DTX1/IO4, DRX0/IO5, DRX1/IO6, ADR1/IO1, ADR2/IO2, IRQ/IO0, PDMCLK/IO7 pins.

Low Level Output Voltage

VIOVDD = 3.00 V, IOL = 1 mA

0.40

VOL

Low Level Output Voltage

VIOVDD = 1.70 V, IOL = 1 mA

0.40

VOL_I2C

5, 7

7 The minimum IOL current is lower than the I2C specification because the SDA and SCL pins are designed for a limited number of I2C attached slave devices.

I2C Low Level Output Voltage

VIOVDD = 3.00 V, IOL = 1.5 mA

0.40

VOL_I2C

5, 7

2C Low Level Output Voltage

VIOVDD = 1.70 V, IOL = 1.5 mA

0.40

CPD

Pin Capacitance

4.8

Negative Bias Switch

IVSSN

Internal VSSN Switch Current

AD2426(W)/AD2427(W)/AD2428(W)

300

IVSSN

Internal VSSN Switch Current

AD2420(W)/AD2429W

100

RVSSN

Internal VSSN On Resistance

1.2

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