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AD2428W Datasheet(PDF) 14 Page - Analog Devices

Part # AD2428W
Description  Automotive Audio Bus A2B Transceiver
PDF  38 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD2428W Datasheet(HTML) 14 Page - Analog Devices

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Rev. B
|
Page 14 of 38
|
January 2020
AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W)
Table 7. I2S Timing
1.8 V
3.3 V
Unit
Parameter
Min
Max
Min
Max
I
2S Slave Timing Requirements (A2B Master)
tBCLKW
BCLK Width
19.5
9.5
ns
tBCLKS
BCLK Period
39.0
19.0
ns
tSIS
1
SYNC Input Setup Before BCLK Sample Edge
2.25
2.25
ns
tSIH
1
SYNC Input Hold After BCLK Sample Edge
2.0
3.0
ns
tRISM
1
DRXn Input Setup Before BCLK Sample Edge
0.5
0.5
ns
tRIHM
1
DRXn Input Hold After BCLK Sample Edge
2.0
1.5
ns
tRISM
1
DRX1 on DTX1 Input Setup Before BCLK Sample Edge
4.0
4.5
ns
tRIHM
1
DRX1 on DTX1 Input Hold After BCLK Sample Edge
0.5
0.5
ns
I
2S Slave Switching Characteristics (A2B Master)
tDODM
2
DTXn Output Delay After BCLK Drive Edge
15.25
12.0
ns
tDOHM
2
DTXn Output Hold After BCLK Drive Edge
3.0
3.0
ns
tDOENM
2
DTXn Data Enable Delay After BCLK Drive Edge
2.0
2.0
ns
tDODIM
2
DTXn Data Disable Delay After BCLK Drive Edge
13.0
8.0
ns
I
2S Master Timing Requirements (A2B Slave)
tRISS
1
DRXn Input Setup Before BCLK Sample Edge
0.0
0.0
ns
tRIHS
1
DRXn Input Hold After BCLK Sample Edge
5.8
2.0
ns
tRISS
1
DRX1 on DTX1 Input Setup Before BCLK Sample Edge
2.5
4.5
ns
tRIHS
1
DRX1 on DTX1 Input Hold After BCLK Sample Edge
2.5
0.5
ns
I
2S Master Switching Characteristics (A2B Slave)
fBCLK
BCLK Output Frequency
3
25.0
50.0
MHz
tBCLKMOJ
BCLK Output Jitter (RMS Cycle to Cycle, fBCLKS = 12.288 MHz)
100
100
ps
tSOL/tSOH
Transmit or Receive BCLK Duty Cycle
0.45
0.550.450.55tBCLK
tSOJ
SYNC Output Jitter (RMS Cycle to Cycle fSYNCM = 48 kHz)
2.2
2.2
ns
tSOD
2
SYNC Output Delay After BCLK Drive Edge
6.5
6.5
ns
tSOHD
2
SYNC Output Hold After BCLK Drive Edge
2.8
4.5
ns
tDODS
2
DTXn Output Delay After BCLK Drive Edge
10.8
9.25
ns
tDOHS
2
DTXn Output Hold After BCLK Drive Edge
5.5
6.0
ns
1 Referenced to sample edge.
2 Referenced to drive edge.
3 When V
IOVDD = 3.3 V, the setup and hold timing at the 50 MHz maximum bit clock rate can be violated when interfacing with other I
2S devices. The timing violations are seen
when the A2B slave node is receiving and A2B master node is transmitting. In these modes, the maximum BCLK frequency of 50 MHz cannot be achieved.



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