Rev. B

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Page 26 of 38

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January 2020

AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W)

152

DRX1/IO6

D_IO

PDM1

(PDM1). This pin serves as the IO6 GPIO pin when DRX1 and PDM1 functions are disabled. The

DRX1/IO6 pin is high impedance by default until configured. The pin returns to high impedance

when the chip resets due to a missing synchronization signal or low supply voltage.

For the AD2420W, AD2426W, and AD2427W, the DRX1 function is not supported.

162

PDMCLK/IO7 D_IO

RRSTRB

PDM Microphone Clock Output.

In master mode, the PDM clock output (PDMCLK) is used to clock PDM microphones. This pin

runs at 64× the SYNC frequency regardless of the BCLK rate used by the host.

When using the PDM interface in slave mode, this pin can still operate as the clock output for

PDM microphones (PDMCLK), but BCLK can also be used.

When PDM functions are disabled, this pin serves as the IO7 GPIO pin. The PDMCLK/IO7 pin can

also be used as a strobe to indicate when reduced rate data is updated (RRSTRB). The

PDMCLK/IO7 pin is high impedance by default until configured. The pin returns to high

impedance when the chip resets due to a missing synchronization signal or low supply voltage.

17

ACM

A_IN

None

Common-Mode Input for Bidirectional, Differential A

18

AN

A_IO

None

Inverted Pin of Bidirectional, Differential A

towards the master. Pin 18 is self biased.

19

AP

A_IO

None

Noninverted Pin of Bidirectional, Differential A

towards the master. Pin 19 is self biased.

20

ATRXVDD

PWR

None

shared 100 nF capacitor and a shared 10 nF capacitor closest to the pin. The pins can be supplied

by VOUT2. Supply the ATRXVDD pin for a master, last slave, or daisy-chained slave.

21

BTRXVDD

PWR

None

Power Supply for A

shared 100 nF capacitor and a shared 10 nF capacitor closest to the pin. The pins can be supplied

by VOUT2. Supply the BTRXVDD pin for a master, last slave, or daisy-chained slave

22

BP

A_IO

None

For the AD2427W, AD2428W, and AD2429W, this is the noninverted pin of bidirectional, differ-

ential A

23

BN

A_IO

None

For the AD2427W, AD2428W, and AD2429W, this is the inverted pin of bidirectional, differential

A

24

BCM

A_IN

None

For the AD2427W, AD2428W, and AD2429W, this is the common-mode input for bidirectional,

differential A

25

VSS

PWR

None

Power Supply Pin for Return Currents. Connect the VSS pin to a low impedance local VSS ground

plane.

26

VSSN

PWR

None

For the AD2427W, AD2428W, and AD2429W, this is the power supply return current connection

for the next slave device. Connect to the inductor that provides the negative bias for the next

slave device. The AD2427W, AD2428W, and AD2429W connect VSSN to the local VSS potential

to sequence power to the next slave devices in the chain. VSSN automatically disconnects under

critical fault conditions.

27

SWP

D_OUT

None

For the AD2427W, AD2428W, and AD2429W, this is the active low open-drain output to drive

the gate of a PMOS switch. The switch is open (SWP pin is high) by default. The switch can be

closed (SWP pin goes low) to sequence power to the next slave devices in the chain. The switch

automatically opens (SWP goes high) under critical fault conditions.

28

SENSE

A_IN

None

Analog input to sense the power supplied to the next slave device. For the AD2420W, AD2426W,

or a last in line AD2427W/AD2428W/AD2429W, connect this pin to local ground through a 33 kΩ

pull-down resistor.

Table 15. AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W) Pin Function Descriptions (Continued)

Pin



No.

Pin Name

Type

Alternate



In this table, the Type is defined as follows: PWR = power/ground, A_IN = analog input, D_OUT = digital output, A_IO = analog input/output,

D_IO = digital input/output, N/A = not applicable.