AD2428W datasheet(5/38 Pages) AD

5 / 38 page

AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W)

Rev. B

Page 5 of 38

January 2020

I2C INTERFACE

The I2C interface in the transceiver provides access to the inter-

nal registers. Operation is not guaranteed above the VI2C_VBUS

specification. The I2C interface has the following features:

• Slave functionality in the A2B master

• Master or slave functionality in the A2B slave

• Multimaster support in the A2B slave

• 100 kbps or 400 kbps rate operation

• 7-bit addressing

• Single-word and burst mode read and write operations

•Clock stretching

All transceivers can be accessed by a locally connected processor

using the 7-bit I2C device address (BASE_ADDR) established by

the logic levels applied to the ADR2/IO2 and ADR1/IO1 pins at

power-on reset, thus providing for up to four master devices

connecting to the same I2C bus. A slave configured transceiver

recognizes only this I2C device address. A master configured

transceiver, however, also recognizes a second I2C device

address for remote access to slave nodes over the A2B bus

(BUS_ADDR). The least significant bit (LSB) of the 7-bit device

address determines whether an I2C data exchange uses the

BASE_ADDR (Bit 1 = 0) to access the transceiver or

BUS_ADDR (Bit 1 = 1) to access a bus node slave transceiver

through a master configured AD2425W transceiver. See the

AD2420(W)/6(W)/7(W)/8(W)/9(W) Automotive Audio Bus A2B

Transceiver Technical Reference for details.

I2S/TDM INTERFACE

The I2S/TDM serial port operates in full-duplex mode, where

both the transmitter and receiver operate simultaneously using

the same critical timing bit clock (BCLK) and synchronization

(SYNC) pins. A2B slave transceivers generate the timing signals

on the BCLK and SYNC output pins. A2B master transceivers

use the same BCLK and SYNC pins as inputs, which are driven

by the host device. The I2S/TDM port includes the following

features:

• Programmable clock and frame sync timing and polarity

• Numerous TDM operating modes

• 16- or 32-bit data width

• Simultaneous operation with PDM port

• Single- or dual-pin input/output (I/O)

Figure 3. A2B Superframe

Figure 4. A2B Bus Synchronous Data Exchange

SYNCH

CONTROL

FRAME

DOWNSTREAM

A2B DATA SLOTS

SYNCH

RESPONSE

FRAME

UPSTREAM

A2B DATA SLOTS

SYNCH

CONTROL

FRAME

SUPERFRAME: 20.83 s FOR 48kHz SAMPLING RATE

MASTER NODE

I2S TX

DATA

I2S RX

DATA

A2B DATA

I2S UPSTREAM DATA N - 2

SLAVE NODE

I2S UPSTREAM DATA N - 1I2S UPSTREAM DATA N

I2S DOWNSTREAM DATA M

I2S DOWNSTREAM DATA M + 1I2S DOWNSTREAM DATA M + 2

I2S UPSTREAM DATA N

I2S UPSTREAM DATA N + 1

I2S UPSTREAM DATA N + 2

I2S DOWNSTREAM DATA M - 2I2S DOWNSTREAM DATA M - 1I2S DOWNSTREAM DATA M

DNSTREAM

A2B DATA

M-1

UPSTREAM

A2B DATA

N-1

DNSTREAM

A2B DATA

UPSTREAM

A2B DATA

DNSTREAM

A2B DATA

M+1

UPSTREAM

A2B DATA

N+1

SUPERFRAME

I2S RX

DATA

I2S TX

DATA

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