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AD2428W Datasheet(PDF) 16 Page - Analog Devices |
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AD2428W Datasheet(HTML) 16 Page - Analog Devices |
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16 / 38 page ![]() Rev. B | Page 16 of 38 | January 2020 AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W) POWER-UP SEQUENCING RESTRICTIONS When externally supplied, VDVDD and VIOVDD must reach at least 90% of specification before VVIN begins ramping. To avoid dam- age to input pins and to ensure correct sampling of the ADR1/ADR2 pins at start-up, VIOVDD must be within specifica- tion before input signals are driven by external devices. Table 8. Power-Up Timing Parameter Min Max Unit Timing Requirements tVIN When Externally Supplied, VDVDD and VIOVDD Must Reach 90% of Specification Before VVIN Begins Ramping >0 ms tPORST Minimum Time Required for VVIN to be Held Below VRST to Assert Power on Reset 25 ms Figure 13. Power-Up Sequencing Timing with Externally Supplied VDVDD and VIOVDD VDVDD | VIOVDD VVIN tVIN tPORST VRST MIN VRSTN MAX |
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