AD2428W datasheet(12/38 Pages) AD

12 / 38 page

Rev. B

Page 12 of 38

January 2020

AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W)

TIMING SPECIFICATIONS

Table 3. Clock and Reset Timing (A2B Master)

Parameter

Min

Typ

Max

Unit

Timing Requirements

fSYNCM

SYNC Pin Input Frequency Continuous Clock

43.6

44.1, 48.0

48.5

kHz

tSYNCIJ

SYNC Pin Input Jitter RMS TIE

0.29

1.0

tSYNCOJ

SYNC Pin Output Jitter RMS TIE

2.6

fSYSBCLK

Bus Clock

1024 × fSYNCM

kHz

tDNSYNCR

Delay from First Missed SYNC to Reset (A2B Master)

0.64

0.74

tDNSCFR

Delay from First Missed SCF to Reset (A2B Slave)

0.64

0.74

tPLK

PLL Lock Time

7.5

1 Only consecutive missed SYNC or SCF transitions for the specified duration result in a reset.

Table 4. Pulse Density Modulation Microphone Input Timing

Parameter

Min

Typ

Max

Unit

Timing Requirements

tRISS

DRXn Input Setup Before BCLK

12.0

tRIHS

DRXn Input Hold After BCLK

tRISS

DRXn Input Setup Before PDMCLK

12.5

tRIHS

DRXn Input Hold After PDMCLK

Switching Characteristics

fBCLK

BCLK/PDMCLK Output Frequency

3.05

3.18

MHz

tBCLKOJ

BCLK/PDMCLK Output Jitter RMS Cycle to Cycle

175

tSOL

BCLK/PDMCLK Output Pulse Width Low

161.0

Table 5. GPIO Timing

Parameter

Min

Typ

Max

Unit

Timing Requirement

tFIPW

Input Pulse Width

tSYSBCLK + 1

Switching Characteristic

tFOPW

Output Pulse Width

tSYSBCLK – 1

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