MAS3506D datasheet(7/52 Pages) MICRONAS

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PRELIMINARY DATA SHEET

MAS 3506D

Micronas

2. Functional Description of the MAS 3506D

2.1. Overview

The hardware of the MAS 3506D consists of a high-

performance RISC Digital Signal Processor (DSP) and

appropriate interfaces for WorldSpace Broadcast

Channel decoding (see Figure 2–1). The internal pro-

cessor works with a memory word length of 20 bits and

an extended range of 32 bits in its accumulators. The

instruction set of the DSP is highly optimized for audio

data compression and decompression. Thus, only very

small areas of internal RAM and ROM are required. All

the data input and output actions are based on a ’non-

cycle-stealing’ background DMA that does not cause

any computational overhead (except for some initial-

ization). The overall function of the MAS 3506D can be

altered by downloading up to 1 kWord of program

code into the internal RAM and executing this code

instead of the built-in firmware ROM code1). Dedicated

clock management hardware supports synchronization

on the transmitted data signal. A DC/DC step-up con-

verter has been integrated for efficient battery-based

operation. Fig. 2–1 shows the building blocks of the

MAS 3506D.

1) Detailed information about downloading is provided

in combination with the MAS 3506D software devel-

opment package or together with the MAS 3506D

software modules available from Micronas.

2.2. Firmware (Internal Program ROM)

The firmware of the MAS 3506D operates on the

Broadcast

Channel

signal

generated

the

DRD 3515A. The MAS 3506D firmware processes the

input signal in four steps.

– Broadcast Channel synchronization

– Broadcast Channel demultiplexing

– MPEG audio decoding

– Frame synchronization and decoding error signals

are provided at output pins of the MAS 3506D.

2.2.1. Broadcast Channel Synchronization

The MAS 3506D analyzes the incoming BC bitstream

and detects the Service Control Header (SCH) pream-

ble. If the preamble is found, the BC-SYNC signal

(available at a MAS 3506D output pin) indicates that

the MAS 3506D is in synchronized state. If synchroni-

zation is lost, the MAS 3506D automatically resets the

BC-SYNC signal and performs an audio soft-mute until

the next SC-header is detected.

Fig. 2–1: Functional overview of the MAS 3506D

OCLK

BC input

Digital Audio

output

Clock

Synthesizer

Volume

Matrix

SCH

buffer

Configuration

Registers

SCH

Synchro-

Service

Component

Selection

Layer 3

Status

Data Buffer

Ancillary

Data

MPEG 1/2/2.5 Layer 3

Decoder

nization

µC

(I2C)

MAS3506D Datasheet(PDF) 7 Page - Micronas

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