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TAS2563 Datasheet(PDF) 4 Page - Texas Instruments

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Part # TAS2563
Description  TAS2563 6.1-W Boosted Class-D Audio Amplifier With Integrated DSP And IV Sense
PDF  127 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TAS2563 Datasheet(HTML) 4 Page - Texas Instruments

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background image
VBST
16
SW
15
GNDB
14
GREG
13
SPII2CZ_MISO
12
SDIN1
11
SDOUT1
10
NC
9
18
19
20
21
22
23
17
2
3
4
5
6
7
PVDD
25
OUT_N
26
GNDP
27
GNDD
28
VSNS_N
29
VBAT
30
VDD
31
32
1
8
24
IOVDD
PDMCLK
NC
PDMD
NC
Not to scale
Figure 5-2. RPP Package 32-pin QFN Top View
Pin Functions
PIN
TYPE
DESCRIPTION
NAME
DSBGA
NO.
QFN NO.
ADDR_SPI
CLK
C4
19
I
I2C Mode - Address selection pin See General I2C operation. SPI Mode - SPI
clock
DREG
B6
2
P
Digital core voltage regulator output. Bypass to GND with a cap. Do not connect
to external load.
FSYNC
B3
5
I
I2S word clock or TDM frame sync for ASI1 and ASI2 channels.
GNDB
E1, E2, E3
14
P
Boost ground. Connect to PCB GND plane.
GNDD
F4
28
P
Digital ground. Connect to PCB GND plane.
GND
E4
N/A
P
Analog ground. Connect to PCB GND plane.
GNDP
E5,E6
27
P
Power stage ground. Connect to PCB GND plane.
GPIO
D6
22
IO
General purpose input-ouput or MCLK base on register configuration.
GREG
D4
13
P
High-side gate CP regulator output. Do not connect to external load.
IOVDD
A6
32
P
3.3-V/1.8-V IOVDD Supply
IRQZ
C5
18
O
Open drain, active low interrupt pin. Pull up to IOVDD with resistor if optional
internal pull up is not used.
OUT_N
F6
26
O
Class-D negative output for receiver channel.
OUT_P
F5
21
O
Class-D positive output for receiver channel.
PDMCLK
A1
9
IO
PDM clock.
TAS2563
SLASET3B – FEBRUARY 2020 – REVISED DECEMBER 2020
www.ti.com
4
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Copyright © 2020 Texas Instruments Incorporated
Product Folder Links: TAS2563



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