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TAS2563 Datasheet(PDF) 84 Page - Texas Instruments |
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TAS2563 Datasheet(HTML) 84 Page - Texas Instruments |
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84 / 127 page ![]() Table 8-120. Interrupt Mask 3 Field Descriptions (continued) Bit Field Type Reset Description 2 Reserved RW 1h Reserved 1 Reserved RW 1h Reserved 0 Reserved RW 1h Reserved 8.5.32 INT_LIVE0 (page=0x00 address=0x1F) [reset=0h] Live interrupt readback. Figure 8-51. INT_LIVE0 Register Address: 0x1F 7 6 5 4 3 2 1 0 INT_LIVE0[7] INT_LIVE0[6] INT_LIVE0[5] INT_LIVE0[4] INT_LIVE0[3] INT_LIVE0[2] INT_LIVE0[1] INT_LIVE0[0] R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 8-121. Live Interrupt Readback 0 Field Descriptions Bit Field Type Reset Description 7 INT_LIVE0[7] R 0h Interrupt due to limiter mute. 0b = No interrupt 1b = Interrupt 6 INT_LIVE0[6] R 0h Interrupt due to limiter infinite hold. 0b = No interrupt 1b = Interrupt 5 INT_LIVE0[5] R 0h Interrupt due to limiter max attenuation. 0b = No interrupt 1b = Interrupt 4 INT_LIVE0[4] R 0h Interrupt due to VBAT below limiter inflection point. 0b = No interrupt 1b = Interrupt 3 INT_LIVE0[3] R 0h Interrupt due to limiter active. 0b = No interrupt 1b = Interrupt 2 INT_LIVE0[2] R 0h Interrupt due to TDM clock error. 0b = No interrupt 1b = Interrupt 1 INT_LIVE0[1] R 0h Interrupt due to over current error. 0b = No interrupt 1b = Interrupt 0 INT_LIVE0[0] R 0h Interrupt due to over temp error. 0b = No interrupt 1b = Interrupt 8.5.33 INT_LIVE1 (page=0x00 address=0x20) [reset=0h] Live interrupt readback. Figure 8-52. INT_LIVE1 Register Address: 0x20 7 6 5 4 3 2 1 0 Reserved Reserved INT_LIVE1[5] INT_LIVE1[4] INT_LIVE1[3] INT_LIVE1[2] INT_LIVE1[1] INT_LIVE1[0] R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h LEGEND: R/W = Read/Write; R = Read only; -n = value after reset TAS2563 SLASET3B – FEBRUARY 2020 – REVISED DECEMBER 2020 www.ti.com 84 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TAS2563 |
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