TAS2563 datasheet(39/127 Pages) TI

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Table 8-17. Digital Input Pull Down Enables (continued)

DESCRIPTION

BIT VALUE

STATE

DIN_PD[7]

Weak pull down for GPIO.

Disabled

Enabled (default)

8.4 Device Functional Modes

8.4.1 PDM Input

The TAS2563 provides one PDM input. Figure 8-11 below illustrates the double data rate nature of the PDM

input. It has two interleaved PDM channels, one sampled by the rising edge and the other by the falling edge of

the clock.

PDM CLK

PDM DATA

Rising

Channel

Falling

Channel

Figure 8-11. PDM Waveform

The PDM inputs are sampled by the PDMCLK pin, which can be configured as either a PDM clock slave input or

a PDM clock master output. The PDM_MIC_EDGE and PDM_MIC_SLV register bits select the sample clock

edge and master/slave mode PDM inputs. In master mode the PDMCLK pin can disable the clocks (and drive a

logic 0) by setting the PDM_GATE_PAD0 register bits low.

When configured as a clock slave, the PDM clock input does not require a specific phase relationship to the

system clock (SBCLK in TDM/I2S Mode), but must be from the same source as audio sample rate. This is

equivalent to 64/32/16 (~3 MHz) or 128/64/32 (~6 MHz) times a single/double/quadruple speed sample rate. The

PDM rate is set by the PDM_RATE_PAD0 .

When PDMCLK pin is configured as a clock master, the TAS2563 will output a 50% duty cycle clock of frequency

that is set by the PDM_RATE_PAD0 and register bit (64/32/16 or 128/64/32 times a single/double/quadruple

speed sample rate).

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TAS2563

SLASET3B – FEBRUARY 2020 – REVISED DECEMBER 2020

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