TAS2563 datasheet(42/127 Pages) TI

Part #	TAS2563

Description	TAS2563 6.1-W Boosted Class-D Audio Amplifier With Integrated DSP And IV Sense

PDF	127 Pages

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Manufacturer	TI [Texas Instruments]

Direct Link	http://www.ti.com

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Table 8-24. PCM SBCLK to FSYNC Ratio (continued)

FS_RATIO[3:0]

SBCLK to FSYNC Ratio

0x4

0x5

0x6

128

0x7

192

0x8

256

0x9

384

0xA

512

0xB-0xE

Reserved

0xF

Error Condition

Figure 8-12 and Figure 8-13 below illustrates the receiver frame parameters required to configure the port for

playback. A frame begins with the transition of FSYNC from either high to low or low to high (set by the

FRAME_START register bit). FSYNC and SDIN are sampled by SBCLK using either the rising or falling edge

(set by the RX_EDGE register bit). The RX_OFFSET[4:0] register bits define the number of SBCLK cycles from

the transition of FSYNC until the beginning of time slot 0. This is typically set to a value of 0 for Left Justified

format and 1 for an I2S format.

MSB

MSB-1

LSB+1

LSB

RX_WLEN

RX_SLEN

RX_OFFSET

SBCLK

FSYNC

SDIN

Figure 8-12. TDM RX Time Slot with Left Justification

TAS2563

SLASET3B – FEBRUARY 2020 – REVISED DECEMBER 2020

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