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TAS2764 Datasheet(PDF) 42 Page - Texas Instruments |
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TAS2764 Datasheet(HTML) 42 Page - Texas Instruments |
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42 / 107 page  Table 8-20. TDM Configuration 4 Field Descriptions (continued) Bit Field Type Reset Description 0 TX_EDGE RW 1h TDM TX launch clock polarity. 0b = Rising edge of SBCLK 1b = Falling edge of SBCLK 8.9.19 TDM_CFG5 (page=0x00 address=0x0E) [reset=42h] Sets TDM TX V-Sense time slot and enable. LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 8-21. TDM Configuration 5 Field Descriptions Bit Field Type Reset Description 7 Reserved R 0h Reserved 6 VSNS_TX RW 1h TDM TX voltage sense transmit 0b = Disabled 1b = Enabled 5-0 VSNS_SLOT[5:0] RW 2h TDM TX voltage sense time slot. 8.9.20 TDM_CFG6 (page=0x00 address=0x0F) [reset=40h] Sets TDM TX I-Sense time slot and enable. LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 8-22. TDM Configuration 6 Field Descriptions Bit Field Type Reset Description 7 Reserved R 0h Reserved 6 ISNS_TX RW 1h TDM TX current sense transmit 0b = Disabled 1b = Enabled 5-0 ISNS_SLOT[5:0] RW 0h TDM TX current sense time slot. 8.9.21 TDM_CFG7 (page=0x00 address=0x10) [reset=04h] Sets TDM TX VBAT1S time slot and enable. LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 8-23. TDM Configuration 7 Field Descriptions Bit Field Type Reset Description 7 VBAT1S_SLEN RW 0h TDM TX VBAT1S time slot length. 0b = Truncate to 8-bits 1b = Left justify to 16-bits 6 VBAT1S_TX RW 0h TDM TX VBAT1S transmit enable. 0b = Disabled 1b = Enabled 5-0 VBAT1S_SLOT[5:0] RW 4h TDM TX VBAT1S time slot. 8.9.22 TDM_CFG8 (page=0x00 address=0x11) [reset=05h] Sets TDM TX TEMP time slot and enable. LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 8-24. TDM Configuration 8 Field Descriptions Bit Field Type Reset Description 7 Reserved R 0h Reserved TAS2764 SLOS998 – DECEMBER 2020 www.ti.com 42 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: TAS2764 |
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