TAS2764 datasheet(23/107 Pages) TI

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The noise gate can be configured with finer resolution at the expense of additional I2C writes. Use NGFR_EN bit

to enable this mode and register bits NGFR_LVL[31:0] to set the fine resolution. The fine resolution hysteresis is

set using NGFR_HYST[18:3] register bits.

Note

When noise gate triggers due to input signal below the threshold, the SAR outputs will be kept at the

levels existing prior to the triggering event.

During Noise Gate mode SAR and DSP are disabled and voltage and temperature measurements

transmited through TDM (SDO) will be at zero.

8.4.2.8 Supply Tracking Limiter with Brown Out Prevention

The TAS2764 contains a supply tracking limiter to control distortion and brownout prevention to mitigate

brownout events. The gain reduction that occurs due to this block can be aligned across multiple devices using

the Inter Chip Gain Alignment feature (Section 8.4.2.9) . The maximum device attenuation set by

DEV_MAX_ATTN[6:0] register bits can be used to limit the combination of the limiter and brownout attenuation

or the Inter Chip Gain Alignment.

The Supply Tracking Limiter (Section 8.4.2.8.1) and the BOP (Section 8.4.2.8.2) are configured independently.

The Inter Chip Gain Alignment, if enabled, keeps multiple device gains in sync if the Supply Tracking Limiter and

BOP need to reduce the gain. However, the BOP will take priority in the device. In order to prevent the Supply

Tracking Limiter and BOP from both making simultaneous adjustments to the system, the Supply Tracking

Limiter and Inter Chip Gain Alignment will be pause once the BOP engages until it fully releases .

Figure 8-5. Limiter and Brown Out Prevention Interaction Diagram

The attenuation applied to the device can be selected to be either the sum of the limiter attenuation (ICLA) and

Brownout attenuation (ICBA) or the maximum of the two of them by setting the ICG_MODE register bit.

8.4.2.8.1 Supply Tracking Limiter

The TAS2764 monitors the PVDD supply voltage and the audio signal to automatically decrease gain when the

audio signal peaks exceed a programmable threshold. This helps prevent clipping and extends playback time

through end of charge battery conditions. The limiter threshold can be configured to track PVDD below a

programmable inflection point with a programmable slope. A minimum threshold sets the limit of threshold

reduction from PVDD tracking.

The limiter is enabled by setting the LIM_EN bit register to high.

Configurable attack rate, hold time and release rate are provided to shape the dynamic response of the limiter

(LIM_ATK_RT[3:0], LIM_HLD_TM[2:0] and LIM_RLS_RT [3:0] register bits).

A maximum level of attenuation applied by the limiter is configurable via the LIM_MAX_ATTN[3:0] register bits. If

the limiter mode is attacking and if it reaches the maximum attenuation, gain will not be reduced any further.

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TAS2764

SLOS998 – DECEMBER 2020

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TAS2764 Datasheet(PDF) 23 Page - Texas Instruments