TAS2764 datasheet(29/107 Pages) TI

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8.5 Operational Modes

8.5.1 Hardware Shutdown

The device enters Hardware Shutdown mode if the SDZ pin is asserted low. In Hardware Shutdown mode, the

device consumes the minimum quiescent current from AVDD, VBAT1S and PVDD supplies. All registers loose

state in this mode and I2C communication is disabled.

In normal shutdown mode if SDZ is asserted low while audio is playing, the device will ramp down volume on the

audio, stop the Class-D switching, power down analog and digital blocks and finally put the device into Hardware

Shutdown mode. If configured in normal shutdown mode with timeout the device will force a hard shutdown after

a timeout set by the configurable shutdown timer (register bits SDZ_TIMEOUT[1:0]). The device can also be

configured for forced hard shutdown and in this case it will not attempt to gracefully disable the audio channel.

The shutdown mode can be controlled using SDZ_MODE[1:0] register bits.

When SDZ is released, the device will sample the ADDR pin and enter the software shutdown mode.

8.5.2 Mode Control and Software Reset

The TAS2764 mode can be configured by writing the MODE[2:0] register bits.

A software reset can be accomplished by setting high the SW_RESET register bit. This bit is self clearing. Once

enabled it will restore all registers to their default values.

8.5.3 Software Shutdown

Software Shutdown mode powers down all analog blocks required to playback audio, but does not cause the

device to loose register state.

The registers are available through I2C interface.

Software Shutdown is enabled by asserting the MODE[2:0] register bits to 3'b010. If audio is playing when

Software Shutdown is asserted, the Class-D will volume ramp down before shutting down. When de-asserted,

the Class-D will begin switching and volume ramp back to the programmed digital volume setting.

8.5.4 Mute

The TAS2764 will ramp down volume of the Class-D amplifier to a mute state by setting the MODE[2:0] register

bits to 3'b001. During mute the Class-D still switches but transmits no audio content. If mute is de-asserted, the

device will ramp back the volume to the programmed digital setting.

8.5.5 Active

In Active Mode the Class-D switches and plays back audio. Speaker voltage and current sensing are operational

if enabled. PDM inputs are also active if enabled. Set the MODE[2:0] register bits to 3'b000 to enter active mode.

8.5.6 Diagnostic

The TAS2764 has a diagnostic generator that can be used without any PCM clocking to the device. If DG_CLK

bits. For sine-wave generation the sampling frequency fs should be first set using the SAMP_RATE[2:0] register

bits.

The programable DC level for diagnostic mode can be set using the DG_DC[31:0] register bits.

To play a DC diagnostic tone set the bits HPF_FREQ_PB[2:0] in register 0x04 to 0h (disabled DC blocker).

8.5.7 Noise Gate

In this mode of operation described in section Section 8.4.2.7 the TAS2764 monitors the signal and powers

down the class-D when signal goes below a threshold.

8.6 Faults and Status

During the power-up sequence, the circuit monitoring the AVDD pin (UVLO) will hold the device in reset

(including all configuration registers) until the supply is valid. The device will not exit hardware shutdown until

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TAS2764

SLOS998 – DECEMBER 2020

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