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TAS2764 Datasheet(PDF) 3 Page - Texas Instruments |
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TAS2764 Datasheet(HTML) 3 Page - Texas Instruments |
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3 / 107 page  5 Pin Configuration and Functions 1 2 3 4 5 A B C D E Not to scale F VSNS_N BST_N OUT_P PGND OUT_N VSNS_P BST_P OUT_P PGND OUT_N GND DREG PVDD_SNS PVDD PVDD SBCLK SDIN IRQZ GND AVDD SDA SCL IOVDD SDZ ICC SDOUT FSYNC BYP_EN ADDR VBAT1S Figure 5-1. YBH Package 30-Ball DSBGA Top View Table 5-1. Pin Functions PIN I/O DESCRIPTION NAME NO. ADDR D4 I Address detect pin. Resistor value at this pin selects the I2C address. See Device Address Selection section. Minimize capacitive loading on this pin and do not connect to any other load. AVDD E5 P Analog power input. Connect to 1.8V supply and decouple to GND with cap. BST_N A2 P Class-D negative bootstrap. Connect a capacitor between BST_N and OUT_N. BST_P B2 P Class-D positive bootstrap. Connect a capacitor between BST_P and OUT_P. DREG C2 P Digital core voltage regulator output. Bypass to GND with a capacitor. Do not connect to external load. FSYNC D2 I TDM Frame Sync. GND E4 P Analog ground. Connect to PCB ground plane. C1 ICC F5 IO Interchip communication pin used to transmit gain alignment. IOVDD F3 P Digital IO Supply. Connect to 1.2V or 1.8 V IO supply and decouple with a capacitor to GND. IRQZ E3 O Open drain, active low interrupt pin. Pull up to IOVDD with resistor if optional internal pull up is not used. BYP_EN D3 O Low voltage signaling pin with open drain output. OUT_N B5 O Class-D negative output. A5 www.ti.com TAS2764 SLOS998 – DECEMBER 2020 Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: TAS2764 |
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