TAS2764 datasheet(28/107 Pages) TI

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8.4.7 Thermal Foldback

The TAS2764 monitors the die temperature and can automatically limit the audio signal when the die

temperature reaches a set threshold. It is recommended to use the thermal fold-back registers to configure this

protection mechanism as the software will perform the necessary math for each register.

Thermal fold-back can be disabled using TFB_EN register bit. If the die temperature reaches the value set by

TF_TEMP_TH[31:0] register bits this feature will begin to attenuate the audio signal to prevent the device from

shutting down due to over-temperature. It will attenuate the audio signal by a value set in TF_LIMS[31:0] register

bits over a range of temperature set by TF_TEMP_TH[31:0] register bits. The thermal fold-back attack is at a

fixed rate of 0.25dB per sample. A maximum attenuation can be specified using register bits

TF_MAX_ATTN[31:0]. However, if the device continue to heat up, eventually the device over-temperature will be

triggered. The attenuation will be held for a number of samples set by register bits TF_HOLD_CNT[31:0], before

the attenuation will begin releasing.

8.4.8 Over Power Protection

The TAS2764 monitors the temperature of the internal power FETs. If the maximum continue power is high and

power FETs temperature goes up above a threshold, an inbuilt protection circuit will shutdown the device.

8.4.9 Clocks and PLL

The device clocking is derived from the SBCLK input clock. The tables below show the valid SBCLK clock

frequencies for each sample rate and SBCLK to FSYNC ratio (for 44.1 kHz and 48 kHz family frequencies).

If the sample rate is properly configured via the SAMP_RATE[2:0] register bits, no additional configuration is

required as long as the SBCLK to FSYNC ratio is valid. The device will detect improper SBCLK frequencies and

SBCLK to FSYNC ratios and volume ramp down the playback path to minimize audible artifacts. After the clock

error is detected, the device will enter a low power halt mode after a time set by CLK_HALT_TIMER[2:0] register

bits if CLK_HALT_EN bit is high. Additionally, the device can automatically power up and down on valid clock

signals if CLK_ERR_PWR_EN register bit is set to high. The device sampling rate should not be changed while

this feature is enabled. In this mode the CLK_HALT_EN bit register should be set high in order for this feature to

work properly.

Table 8-3. Supported SBCLK Frequencies (48 kHz based sample rates)

Sample Rate

(kHz)

SBCLK to FSYNC Ratio

125

48 kHz

768 kHz

1.152 MHz

1.536 MHz

2.304 MHz

3.072 MHz

4.608 MHz

6 MHz

96 kHz

1.536 MHz

2.304 MHz

3.072 MHz

4.608 MHz

6.144 MHz

9.216 MHz

12 MHz

Sample Rate

(kHz)

SBCLK to FSYNC Ratio

128

192

250

256

384

500

512

48 kHz

6.144 MHz

9.216 MHz

12 MHz

12.288 MHz

18.432 MHz

24 MHz

24.576 MHz

96 kHz

12.288 MHz

18.432 MHz

24 MHz

24.576 MHz

Table 8-4. Supported SBCLK Frequencies (44.1 kHz based sample rates)

Sample Rate

(kHz)

SBCLK to FSYNC Ratio

125

44.1 kHz

705.6 kHz

1.0584 MHz

1.4112 MHz

2.1168 MHz

2.8224 MHz

4.2336 MHz

5.5125 MHz

88.2 kHz

1.4112 MHz

2.1168 MHz

2.8224 MHz

4.2336 MHz

5.6448 MHz

8.4672 MHz

11.025 MHz

Sample Rate

(kHz)

SBCLK to FSYNC Ratio

128

192

250

256

384

500

512

44.1 kHz

5.6448 MHz

8.4672 MHz

11.025 MHz

11.2896 MHz

16.9344 MHz

22.05 MHz

22.5792 MHz

88.2 kHz

11.2896 MHz

16.9344 MHz

22.05 MHz

22.5792 MHz

TAS2764

SLOS998 – DECEMBER 2020

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