TAS2764 datasheet(27/107 Pages) TI

27 / 107 page

8.4.3 SAR ADC

An ADC monitors PVDD voltage, VBAT1S voltage and die temperature. The results of these conversions are

available via register readback (PVDD_CNV, VBAT1S_CNV and TMP_CNV register). PVDD and VBAT1S

voltage conversions are also used by the limiter and brown out prevention blocks.

The ADC runs at a fixed 667 kHz sample rate (1.5 µs per conversion) interleaved between PVDD voltage and

die temperature measurements. This gives an effective sample rate of 333 kHz (3 µs per conversion) with a

latency of 1 sample (1.5 µs). It results in a worst case measurement latency of 4.5 µs. Actual PVDD and

VBAT1S voltages are calculated by dividing the PVDD_CNV[11:0] and VBAT1S_CNV[11:0] decimal values of

TMP_CNV[7:0] register bits. The supply voltages PVDD and VBAT1S can be filtered using the proper setting of

the SAR_FLT[1:0] register bits but will increase measurement latency. The register bits content should always be

read from MSB to LSB.

8.4.4 Current and Voltage (IV) Sense

The TAS2764 provides speaker voltage and current sense measurements for real time monitoring of

loudspeaker behavior. The VSNS_P and VSNS_N pins should be connected after any ferrite bead filter (or

directly to the OUT_P and OUT_N connections if no EMI filter is used). The V-Sense connections eliminate

voltage drop error due to packaging, PCB interconnect or ferrite bead filter resistance. The V-sense connections

are also used for Section 8.4.5 to correct for any voltage drop induced gain error or non-linearity due to the

ferrite bead. It should be noted that any interconnect resistance after the VSNS terminals will not be corrected

for, so it is advised to connect the sense connections as close to the load as possible.

The voltage and current sense ADCs have a DC blocking filter. This filter can be disabled using the

HPF_FREQ_REC[2:0] register bits.

I-Sense and V-Sense can be powered down by asserting the ISNS_PD and VSNS_PD register bits respectively.

When powered down, the device will return null samples for the powered down block.

8.4.5 Post Filter Feed-Back (PFFB)

The device support post-filter feedback by closing the amplifier feedback loop after the external filter. The

feedback is applied using the VSNS_N and VSNS_P terminals of the device. This feature can be disabled using

the PFFB_EN register bit (if an external filter that violates the amplifier loop stability is implemented). When

PFFB is disabled, the feedback will be internally routed from the OUT_N and OUT_P pins of the device.

In the PFFB mode of operation the following conditions have to be met: ω0>10MHz and ω0/Q>2.5MHz (ω0 and

Q are the cutoff frequency and the quality factor of the external filter).

When using PFFB with external LC filtering overshoot might occur at the speaker terminals. It is recommended

to connect resistors (see Section 9.2) between speaker terninals and VSNS pins to protect internal diodes. As an

example,1 kΩ resistors will reduce the amplifier gain by 0.6% (the external resistors will appear in parallel with

the internal 10 kΩ resistors between OUT and VSNS pins).

8.4.6 Load Diagnostics

The TAS2764 can check the speaker terminal for an open or short. This can be used to verify the continuity of

the speaker or the traces to the speaker. The entire operation is performed by the TAS2764 and result is

reported using the IRQZ pin or by reading over I2C bus on completion. The load diagnostics can be performed

using external audio clock (register bit LDG_CLK=0) or the internal oscillator (LDG_CLK=1).

The speaker open (UT) and short (LT) thresholds are configured using the respective LDG_RES_UT[31:0] and

LDG_RES_LT[31:0] register bits. The diagnostic is run by selecting one of the load diagnostic modes set by

MODE[2:0] register bits. The load diagnostic can be run before transitioning to active mode or stand-alone

returning to software shutdown when complete. When the load diagnostics is run it will play a 22kHz at -35dBFS

for 100ms and measure the resistance of the speaker trace. The result is averaged over the time specified by

the LDG_AVG[1:0] register bits. The measured speaker impedance can be read from LDS_RES_VAL[31:0]

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TAS2764

SLOS998 – DECEMBER 2020

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