TAS2764 datasheet(20/107 Pages) TI

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by setting PVDD_SLEN register bit. The Die temperature and gain are both 8-bit precision and are transmitted in

a single time slot.

The time slot register for each sample stream defines where the MSB transmission begins. For instance, if

VSNS_SLOT[5:0] register bits are set to 2 (decimal), the upper 8 MSBs will be transmitted in time slot 2 and the

lower 8 LSBs will be transmitted in time slot 3. Each sample stream can be individually enabled or disabled by

using VSNS_TX and ISNS_TX register bits. This is useful to manage limited TDM bandwidth since it may not be

necessary to transmit all streams for all devices on the bus.

It is important to ensure that time slot assignments for actively transmitted sample streams do not conflict. For

instance, if VSNS_SLOT[5:0] bits are set to 2 (decimal) and ISNS_SLOT[5:0] bits are set to 3 (decimal), the

lower 8 LSBs of voltage sense will conflict with the upper 8 MSBs of current sense. This will produce

unpredictable transmission results in the conflicting bit slots (i.e. the priority is not defined).

When two or more devices are connected to the same SDOUT pin the slot assignment of the various devices

must be kept exclusive to avoid any contention. This constraint is applicable to both Software Shutdown and

Active Mode. Devices should not be programmed to transmit on the same slot.

The current and voltage values are transmitted at the full 16-bit measured values by default. The

IVMON_LEN[1:0] register bits can be used to transmit only the 8 MSB bits in one slot or 12 MSB bits values

across multiple slots. The special 12-bit mode is used when only 24-bit I2S/TDM data can be processed by the

host processor. The device should be configured with the voltage-sense slot and current-sense slot off by 1 slot

and will consume 3 consecutive 8-bit slots. In this mode the device will transmit the first 12 MSB bits followed by

the second 12 MSB bits specified by the preceding slot.

If time slot selections place transmission beyond the frame boundary, the transmitter will truncate transmission at

the frame boundary.

The time slots for VBAT1S, PVDD and TEMP measurements are set using VBAT1S_SLOT[5:0],

PVDD_SLOT[5:0] and TEMP_SLOT[5:0] register bits. To enable sample stream register bits VBAT1S_TX,

PVDD_TX and TEMP_TX must be set high. The slot length is selected by VBAT1S_SLEN, PVDD_SLEN and

TEMP_SLEN register bits.

For TDM final processed audio slot, enable and length settings use AUDIO_SLOT[5:0], AUDIO_TX and

AUDIO_SLEN register bits.

Information about status of slots can be find in STATUS_SLOT[5:0] register bits. STATUS_TX register bit set

high enables the status transmit.

The slot configuration for the TX limiter gain reduction can be set between 0 (default) and 63 by setting

GAIN_SLOT[5:0] register bits. It is used for the Section 8.4.2.9 and can be either over the TDM Bus or Section

8.4.2.9.1. To use this feature, the register bit GAIN_TX needs to be set high (Enable).

8.4.2 Playback Signal Path

8.4.2.1 High Pass Filter

Excessive DC and low frequency content in audio playback signal can damage loudspeakers. The TAS2764

employs a high-pass filter (HPF) to prevent this from occurring for the PCM playback path. The

HPF_FREQ_PB[2:0] register bits set the corner frequencies of HPF. The filter can be bypassed by setting the

8.4.2.2 Amplifier Inversion

The device will output a non-inverted signal to the OUT_P and OUT_N pins. The output can be inverted with

respect to the digital input value by setting the AMP_INV register bit to high.

8.4.2.3 Digital Volume Control and Amplifier Output Level

The gain from audio input to speaker terminals is controlled by setting the amplifier’s output level and digital

volume control (DVC).

Amplifier output level settings are programmed using AMP_LEVEL[4:0] register bits. The levels are presented in

the Register Map in dBV (dB relative to 1 Vrms), with a full scale digital audio input (0 dBFS) and the DVC set by

TAS2764

SLOS998 – DECEMBER 2020

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