TAS2764 datasheet(22/107 Pages) TI

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When the input was initially above the programmed threshold set by LVS_FTH[4:0] register bits the Class D was

supplied by PVDD rail. If the signal level drops below this threshold for longer than the hysteresis time defined by

LVS_HYS[3:0] bits the Class-D supply will switch to VBAT1S.

The BYP_EN pin will be asserted (open drain released). All values of LVS_HYS[3:0] bit settings will ensure the

remaining samples will be output before BYP_EN is asserted. When multiple devices have BYP_EN pin

connected together, any device requiring a supply voltage higher than the threshold will pull the open drain

output low.

When the signal level crosses above the programmed threshold set by LVS_FTH[4:0] bits the Class-D supply

will switch to PVDD.

The open-drain BYP_EN pin will be de-asserted (actively pulling the output low) after a delay programmed by

the LVS_DLY[1:0] register bits . The Y Bridge will switch from VBAT1S to PVDD after a delay programmed by

the CDS_DLY[1:0] register bits.

LVS threshold is set based on the output signal level and is measured in dBFS.

The LVS threshold can alternately be configured to be a value relative to the VBAT1S voltage. To use the

alternate configuration set the LVS_TMODE bit to high and use the LVS_RTH[3:0] register bits for setting the

threshold.

In the case of threshold relative to VBAT1S the class D will swich to VBAT1S for output signal meeting the

following condition: VOUT<VBAT1S*CD_EFF - LVS_RTH, where CD_EFF is set by registers 48h-4Bh from page

0x04 and LVH_RTH is set by bits [3:0] of register 6Ah from page 0x00.

The LVS fixed thresholds, when CDS_MODE[1:0]=11 (PWR_MODE2 and PWR_MODE5 from Section 12.1),

can be set using register bits LVS_FTH_LOW[1:0]. When CDS_MODE[1:0]=00 (PWR_MODE1 and

PWR_MODE3 from Section 12.1) the thresholds should be set with register bits LVS_FTH[4:0].

8.4.2.6 Y-Bridge

The TAS2764 Class-D output uses a Y-Bridge configuration to improve efficiency during playback. The Section

8.4.2.5 is internally used to select between the PVDD and VBAT1S supplies. This feature is enabled by setting

CDS_MODE[1:0] bits to 2'b00 when both PVDD and VBAT1S are supplied to the device. If not configured to Y-

bridge mode the device will use only the selected supply for class-D output even if clipping would otherwise

occur. The device can operate using only PVDD to supply class-D output. In this configuration the VBAT1S can

be provided from external supply (register bit VBAT1S=0) or generated by an internal LDO (register bit

VBAT1S=1). In this case CDS_MODE[1:0] bits should be set to 2'b10. The TAS2764 Y-Bridge with Low Power

on VBAT1S can be used to switch to the VBAT1S rail only at very low power when close to idle. This will reduce

the class-D output swing when near idle and limit the current requirements of the VBAT1S supply. Set the

CDS_MODE[1:0] register to 2'b11 for this mode.

See Section 12.1 for details on programming the power modes.

The change to the class-D supply determined by the Section 8.4.2.5 can have a delay programed by

CDS_DLY[1:0] register bits.

When in Y-Bridge mode, if the PVDD falls below (VBAT1S+4V) level the Y-bridge will stop switching between

supplies and will remain on the PVDD supply.

8.4.2.7 Noise Gate

The TAS2764 has a noise-gate feature that monitors the input signal and powers down the class-D when the

signal goes below the set threshold set by NG_LVL[1:0] bits for longer than the time set by NG_HYST[1:0]

samples applied to the audio input interface reach the class-D bridge. This feature is enabled by setting NG_EN

bit to high. Once enabled it is able to power up and down the channel within the device processing delay

requiring no additional external control. Volume ramping can be also used during noise gate operations by

setting NG_DVR_EN bit to low.

TAS2764

SLOS998 – DECEMBER 2020

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