TAS2764 datasheet(17/107 Pages) TI

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Table 8-2. I2C Address Selection

I2C SLAVE ADDRESS

ADDR PIN

0x70

Short to GND

0x72

470 Ω to GND

0x74

470 Ω to AVDD

0x76

2.2k Ω to GND

0x78

2.2k Ω to AVDD

0x7A

10 kΩ to GND

0x7C

10 kΩ to AVDD

0x7E

Short to AVDD

The TAS2764 has a global 7-bit I2C address 0x80. When enabled, the device will additionally respond to I2C

commands at this address regardless of the ADDR pin settings. This is used to speed up device configuration

when using multiple TAS2764 devices and programming similar settings across all devices. The I2C ACK /

NACK cannot be used during the multi-device writes since multiple devices are responding to the I2C command.

The I2C CRC function should be used to ensure each device properly received the I2C commands. At the

completion of writing multiple devices using the global address, the CRC at I2C_CKSUM register should be

checked on each device using the local address for a proper value. The global I2C address can be disabled

using I2C_GBL_EN register bit. The I2C address is detected by sampling the ADDR pin when SDZ pin is

released. Additionally, the address may be re-detected by setting I2C_AD_DET register bit high after power up

and the ADDR pin will be re-sampled.

8.3.2 General I2C Operation

The I2C bus employs two signals, SDA (data) and SCL (clock), to communicate between integrated circuits in a

system using serial data transmission. The address and data 8-bit bytes are transferred most-significant bit

(MSB) first. In addition, each byte transferred on the bus is acknowledged by the receiving device with an

acknowledge bit. Each transfer operation begins with the master device driving a start condition on the bus and

ends with the master device driving a stop condition on the bus. The bus uses transitions on the data terminal

(SDA) while the clock is at logic high to indicate start and stop conditions. A high-to-low transition on SDA

indicates a start, and a low-to-high transition indicates a stop. Normal data-bit transitions must occur within the

low time of the clock period.

The master generates the 7-bit slave address and the read/write (R/W) bit to open communication with another

device and then waits for an acknowledge condition. The device holds SDA low during the acknowledge clock

period to indicate acknowledgment. When this occurs, the master transmits the next byte of the sequence. Each

device is addressed by a unique 7-bit slave address plus R/W bit (1 byte). All compatible devices share the

same signals via a bi-directional bus using a wired-AND connection.

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TAS2764

SLOS998 – DECEMBER 2020

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