PC8374L datasheet(196/239 Pages) NSC

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9.0 Legacy Functional Blocks (Continued)

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Revision1.1

9.3 SERIAL PORT 1 (SP1)

9.3.1

General Description

The Serial Port functional block supports serial data communication with a remote peripheral device or modem using a wired

interface. The Serial Port can function in one of three modes:

● 16450-Compatible mode (Standard 16450)

● 16550-Compatible mode (Standard 16550)

● Extended mode

Extended mode provides advanced functionality for the UART.

The Serial Port provides receive and transmit channels that can operate concurrently in full-duplex mode. It performs all

functions required to conduct parallel data interchange with the system and composite serial data exchange with the external

data channel, including:

● Format conversion between the internal parallel data format and the external programmable composite serial format

● Serial data timing generation and recognition

● Parallel data interchange with the system using a choice of bidirectional data transfer mechanisms

● Status monitoring for all phases of communication activity

● Complete MODEM-control capability.

Existing 16550-based legacy software is completely and transparently supported. Module organization and specific fallback

mechanisms switch the module to 16550-Compatible mode on reset or when initialized by 16550 software.

9.3.2

Four register banks, each containing eight registers, control Serial Port operation. All registers use the same 8-byte address

space to indicate offsets 00h through 07h. The active bank must be selected by the software.

The register bank organization enables access to the banks as required for activation of all module modes, while maintaining

transparent compatibility with 16450 or 16550 software.

The Bank Selection register (BSR) selects the active bank and is common to all banks as shown in Figure 38. Therefore,

each bank defines seven new registers.

The default bank selection after system reset is 0.

Table 67. Parallel Port Bitmap Summary for Second Level Offset

Bits

Second

Level

Offset

Mnemonic

7654321

00h

Control0

Reserved

DCR

Live

Freeze Bit

Reserved

EPP

Time-Out

Interrupt

Mask

02h

Control2

SPP Com-

patibility

Channel

Address

Enable

Reserved

Revision

1.7 or 1.9

Select

Reserved

04h

Control4

Reserved

PP DMA Request Inactive Time

Reserved

PP DMA Request Active Time

05h

PP Confg0

Bit 3 of

CNFGA

Demand

DMA

Enable

ECP IRQ Channel Number

Internal

Pull-Up or

Pull-Down

ECP DMA Channel

Number

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