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PC8374L Datasheet(PDF) 194 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part # PC8374L
Description  SensorPathTM SuperI/O with Glue Functions
PDF  239 Pages
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Manufacturer  NSC [National Semiconductor (TI)]
Direct Link  http://www.national.com
Logo NSC - National Semiconductor (TI)

PC8374L Datasheet(HTML) 194 Page - National Semiconductor (TI)

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9.0 Legacy Functional Blocks (Continued)
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194
Revision1.1
9.2 PARALLEL PORT
9.2.1
General Description
The Parallel Port supports all IEEE1284 standard communication modes:
● Compatibility (known also as Standard or SPP)
● Bi-directional (known also as PS/2)
● FIFO
● EPP (known also as Mode 4)
● ECP (with an optional Extended ECP mode)
9.2.2
Parallel Port Register Map
The Parallel Port includes two groups of runtime registers, as follows:
• A group of 21 registers at first level offset, sharing 14 entries. Three of these registers (at offsets 403h, 404h and 405h)
are used only in Extended ECP mode.
• A group of four registers, used only in Extended ECP mode, accessed by a second level offset.
EPP and second level offset registers are available only when the base address is 8-byte aligned.
The desired mode is selected by the ECR runtime register (offset 402h). The selected mode determines which runtime reg-
isters and which address bits are used for the base address. See Tables 64 and 65 for a listing of all registers, their offset
addresses and the associated modes. All registers are VDD3 powered.
Table 64. Parallel Port Registers at First Level Offset
Offset
Mnemonic
Mode(s)
Register Name
Type
00h
DATAR
0,1
Data
R/W
AFIFO
3
ECP FIFO (Address)
W
DTR
4
Data (for EPP)
R/W
01h
DSR
All, except 4
Status
RO
STR
4
Status (for EPP)
RO
02h
DCR
All, except 4
Control
R/W
CTR
4
Control (for EPP)
R/W
03h
ADDR
4
EPP Address
R/W
04h
DATA0
4
EPP Data Port 0
R/W
05h
DATA1
4
EPP Data Port 1
R/W
06h
DATA2
4
EPP Data Port 2
R/W
07h
DATA3
4
EPP Data Port 3
R/W
400h
CFIFO
DFIFO
TFIFO
CNFGA
2
3
6
7
PP Data FIFO
ECP Data FIFO
Test FIFO
Configuration A
W
R/W
R/W
RO
401h
CNFGB
7
Configuration B
RO
402h
ECR
All
Extended Control
R/W
403h
EIR1
1. These registers are extended to the standard IEEE1284 registers. They are
only accessible when enabled by bit 4 of the Parallel Port Configuration register
(see Section 3.9.3 on page 64).
0,1,2,3
Extended Index
R/W
404h
EDR1
0,1,2,3
Extended Data
R/W
405h
EAR1
0,1,2,3
Extended Auxiliary Status
R/W
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