PC8374L datasheet(213/239 Pages) NSC

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10.0 Device Characteristics (Continued)

Revision 1.1

213

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10.1.4 Power Consumption under Recommended Operating Conditions

10.1.5 Voltage Thresholds

10.2 DC CHARACTERISTICS OF PINS, BY I/O BUFFER TYPES

The following tables summarize the DC characteristics of all device pins described in Section 1.2 on page 15. The characteristics

describe the general I/O buffer types defined in Table 1 on page 15. For exceptions, refer to Section 10.2.13 on page 217. The

DC characteristics of the LPC interface meet the PCI Local Bus Specification (Rev 2.2 December 18, 1998) for 3.3V DC signaling.

10.2.1 Input, TTL Compatible

Symbol: INT

Symbol

Parameter

Conditions1

1. All parameters specified for 0

°C ≤ TA ≤ 70°C; VDD3 and VSB3 = 3.3V ±10% unless otherwise specified.

Typ

Max2

2. Not tested. Guaranteed by characterization.

Unit

IDD3

VDD3 Average Supply Current

VIL = 0.5V, VIH = 2.4V, No Load

IDD3LP

VDD3 Quiescent Supply Current in

Low Power Mode3

3. All the modules disabled; no LPC bus activity.

VIL =VSS,VIH =VDD3, No Load

0.5

0.8

ISB3

VSB3 Average Supply Current

VIL = 0.5V, VIH = 2.4V, No Load

ISB3LP

VSB3 Quiescent Supply Current in

Low Power Mode3

VIL =VSS,VIH =VSB3, No Load

TBD

IBAT

VBAT Battery Supply Current

VDD3,VSB3 =0V,VBAT =3V

0.2

0.4

µA

Symbol

Parameter1

1. All parameters speciﬁed for 0

°C

≤ T

≤ 70°C.

Min2

2. Not tested. Guaranteed by characterization.

Typ

Max2

Unit

VDD3ON

VDD3 Detected as Power-on

2.3

2.6

2.9

VDD3OFF

VDD3 Detected as Power-off

2.1

2.5

2.8

VSB3ON

VSB3 Detected as Power-on

2.3

2.6

2.9

VSB3OFF

VSB3 Detected as Power-off

2.1

2.5

2.8

VBATLOW

VBAT Detected as “Low”

2.3

Symbol

Parameter

Conditions

Min

Max

Unit

VIH

Input High Voltage

2.0

5.51

1. Not tested. Guaranteed by design.

VIL

Input Low Voltage

−0.51

0.8

IIL

2. Input leakage current includes the output leakage of the bi-directional buffers with TRI-STATE outputs.

Input Leakage Current

0<VIN <VSUP

3. VSUP is VDD3 or VSB3 according to the input power well.

±1

µA

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