PC8374L datasheet(222/239 Pages) NSC

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10.0 Device Characteristics (Continued)

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222

Revision1.1

10.4.3 Clock Timing

High-Frequency Clock Timing

Figure 49. High-Frequency Clock Waveform Timing

Figure 50. CLOCKI14 and Internal 48 MHz Clock Timing

Symbol Figure

Clock Input Parameters

Reference

Conditions

CLOCKI14

Units

Min

Typ

Max

tCH

Clock High Pulse Width1

1. Not tested. Guaranteed by design.

tCL

Clock Low Pulse Width1

tCP

Clock Period1 (50%-50%)

69.14

69.84

70.54

FCK

−

Clock Frequency

FCKTYP − 1%

14.31818

FCKTYP +1%

MHz

tCR

Clock Rise Time1 (VIL to VIH)

2. Recommended value.

tCF

Clock Fall Time1 (VIH to VIL)

tCE

Clock Generator Enable

RE PCI_RESET

to Clock Generator

enabled

µs

Sym. Fig.

Internal Clock Parameter

Reference

Conditions

INT48M

Units

Min

Typ

Max

tCP

49 Clock Period1 (50%-50%)

1. Not tested. Guaranteed by characterization.

20.83

FCK

− Clock Frequency

MHz

t48MD

50 Clock Wake-Up Time1

After Clock

Generator enabled

500

µs

tCL

tCP

tCH

VIH

VIL

VIH

tCF

tCR

CLOCKI14

(14.31818 MHz)

48 MHz Clock

VDD3 (Power)

VDD3ONmin

tCP (CLOCKI14)

CKVALID bit

(Internal)

Enable Clock Generator

(Internal)

t48MD

tCP (48 MHz)

(Internal)

PCI_RESET

tCE

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PC8374L Datasheet(PDF) 222 Page - National Semiconductor (TI)

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