PC8374L datasheet(142/239 Pages) NSC

142 / 239 page

8.0 Health Management (HM) (Continued)

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142

Revision1.1

8.4.1

HM Address Register (HMADDR)

Power Well: VDD3

Location:

Offset 00h

Type:

R/W

8.4.2

HM Data Register (HMDATA)

Power Well: VDD3

Location:

Offset 01h

Type:

R/W

8.4.3

HM Status and Command Register (HMSTS)

Power Well: VDD3

Location:

Offset 02h

Type:

Varies per bit

Bit

76543210

Name

ADDR

Reset

00000

Bit

Description

7-0

ADDR. Address of the HM register to be accessed (valid addresses appear in the address column in Table 54 on

page 153). An exception are the Status Register 1-3 (addresses 41h, 42h and 73h respectively), which are disabled

for access by LPC bus (reserved). Read access to reserved or undefined registers (not a valid address) returns 0.

Write access to reserved or undefined registers is ignored.

ADDR field can be updated only when the BUSY bit in HMSTS register (see Section 8.4.3 on page 142) is 0; oth-

erwise, the transaction will have unpredictable results

Bit

76543210

Name

DATA

Reset

00000000

Bit

Description

7-0

DATA. Data to be read or written from/to the accessed HM register, whose address is ADDR in HMADDR register.

Writing to this register automatically triggers the access to the HM register.

Writing the DATA field while the BUSY bit in HMSTS register is 1 is ignored; reading the DATA field while the BUSY

bit is 1 returns unpredictable data.

Bit

76543210

Name

Reserved

START_RD

BUSY

Reset

00000000

Bit

Type

Description

7-2

Reserved.

1WO

START_RD. Writing 1 to this bit initiates a read access from the HM register with address HMADDR.AD-

DR. Writing 1 to START_RD is allowed only when BUSY bit is 0; otherwise, the write can have unpredict-

able results.

0RO

BUSY. HM Interface busy.

0: HMDATA register contains valid read data or HM is ready for write access

1: HM is busy

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