PC8374L datasheet(140/239 Pages) NSC

140 / 239 page

8.0 Health Management (HM) (Continued)

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When the START bit in Configuration register is 0, sensor monitoring is disabled. However, following VSB3 power-up, and after

the READY bit becomes 1, Temperature Zone1 is monitored regardless of the state of the START bit. If the temperature data

of Temperature Zone1 is above the default value of the Temperature Critical Limit Zone1 register (+110

°C), ETC is asserted

turning the Main power supply off. In addition, the CRIT1_ERR bit in Status Register 3 is set to 1. This feature protects the CPU

from overheating at VSB3 power-up before the HM is configured by the software for the first time.

The LOCK_LIM bit in the Monitoring Control Register (see Section 8.5.54 on page 176) can lock the Limit registers.

8.3 HM SMBUS ACCESS

This section describes the SMBus transactions protocol used by the HM (see also Section 8.2.1 on page 127).

8.3.1

Write Transaction

This transaction writes a byte of data to an HM register. The specific register is accessed using an 8-bit offset address.

8.3.2

Read Transaction

This transaction reads a byte of data from an HM register. The specific register is accessed using an 8-bit offset address.

This transaction is executed in two stages:

1. The master executes an SMBus write transaction, which conveys the Offset Address information to the HM. During this

stage, the data is read from the specific register into a read buffer. This stage has no Stop condition.

2. Following a Restart condition, the master executes an SMBus read transaction. During this stage the data is transferred

from the read buffer to the master.

Slave Address

Offset Address

Data

(S.A, Write)

(OA7-OA0)

(Command)

= Start condition

= ACK by slave

= Stop condition

Slave Address

Data

(S.A, Write)

(

Command)

= Start condition

= Restart condition

= Stop condition

Slave Address

(S.A, Read)

= ACK by slave

A = ACK by master

= NACK by master

Offset Address

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PC8374L Datasheet(PDF) 140 Page - National Semiconductor (TI)

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