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PC8374L Datasheet(PDF) 137 Page - National Semiconductor (TI) |
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PC8374L Datasheet(HTML) 137 Page - National Semiconductor (TI) |
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137 / 239 page ![]() 8.0 Health Management (HM) (Continued) Revision 1.1 137 www.national.com Figure 33. Soft Spin-Up and Soft Speed-Up Example Figure 34. Soft Slow-Down and Soft Stop Example Other Features The FANPWM frequency is configured by the FREQ field in the Zone ‘n’ Auto Speed Range and FANPWMn Frequency reg- isters. The FANPWM signal polarity (whether 0% duty-cycle represents a low-level or a high-level signal) is configured by INV bit in the FANPWMn Control Configuration registers (see Section 8.5.76 on page 187). INV bit is write-only; its value is reflected in the respective FANOUTn_INV bit in the HMCFG1 register (see Section 3.15.3 on page 79), which is read-only. FANOUTn_INV bit is powered by VBAT, thus preserving the polarity of the FANPWM signal during power failures (i.e., when VSB3 power is off). Duty Cycle Time 85% 35% 20 21 22 12 13 23 23 Spin-up end by speed Spin-up end by time Minimum Duty Cycle Soft Speed-Up Cycle “a” 0% 1 10 11 Duty 19 13 14 12 26 27 25 16 24 15 13 (PWM_MIN) 24 25 Time 85% 57% Soft Slow-Down Soft Stop 0% Cycle “a” Duty 8 9 1 6 7 17 18 16 Cycle “b” Duty 20 21 19 23 22 24 27 26 25 Duty Cycle 18.75% Minimum Duty Cycle (PWM_MIN) Winbond Electronics Corp. Advanced PC Product Center |
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