PC8374L datasheet(141/239 Pages) NSC

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8.0 Health Management (HM) (Continued)

Revision 1.1

141

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8.4 HM LPC ACCESS REGISTERS

The HM LPC Access Registers, described in this section, can be accessed by the host through the LPC Bus. The offsets of

these registers are related to the base address determined by the Base Address registers at Index 60-61h in the HM device

configuration (see Section 3.15 on page 79).

The following abbreviations are used to indicate the register type:

• R/W

= Read/Write.

• RO

= Read-Only.

• WO

= Write-Only. Reading from the bit returns 0.

• R/W1C =Read/Write 1 to Clear. Writing 1 to a bit clears it. Writing 0 has no effect.

Read/Write Operations

The HM registers are used for write and read accesses as follows:

• Write operation:

1. Poll HMSTS.BUSY bit until it is 0.

2. Write the address (index) of the target HM register to HMADDR register.

3. Write the data value to HMDATA register. In response HMSTS.BUSY is set.

4. The transaction is completed when HMSTS.BUSY returns to 0.

• Read operation:

1. Poll HMSTS.BUSY bit until it is 0.

2. Write the address (index) of the target HM register to HADDR register.

3. Set HMSTS.STRT_RD to initiate read transaction. In response HMSTS.BUSY is set.

4. Poll HMSTS.BUSY bit until it is 0.

5. Read HMDATA register.

Table 53. HM LPC Access Registers

Offset

Mnemonic

Name

Type

Power

Well

Section

00h

HMADDR

HM Address Register

R/W

VDD3

8.4.1

01h

HMDATA

HM Data Register

R/W

VDD3

8.4.2

02h

HMSTS

HM Status and Command Register

Varies per bit

VDD3

8.4.3

03h

HMINT_STS1

HM Interrupt Status Register 1

R/W1C

VSB3

8.4.4

04h

HMINT_STS2

HM Interrupt Status Register 2

R/W1C

VSB3

8.4.5

05h

HMINT_EN1

HM Interrupt Enable Register 1

R/W

VDD3

8.4.6

06h

HMINT_EN2

HM Interrupt Enable Register 2

R/W

VDD3

8.4.7

07h

HMSENS_STS1 HM Sensor Status Register 1

VSB3

8.4.8

08h

HMSENS_STS2 HM Sensor Status Register 2

VSB3

8.4.9

09h

HMINT_STS3

HM Interrupt Status Register 3

R/W1C

VSB3

8.4.10

0Ah

HMINT_EN3

HM Interrupt Enable Register 3

R/W

VDD3

8.4.11

0Bh

HMSENS_STS3 HM Sensor Status Register 3

VSB3

8.4.12

0Ch

HMS_EN1

HM SMI/SCI Enable Register 1

R/W

VSB3

8.4.13

0Dh

HMS_EN2

HM SMI/SCI Enable Register 2

R/W

VSB3

8.4.14

0Eh

HMS_EN3

HM SMI/SCI Enable Register 3

R/W

VSB3

8.4.15

0Fh

SMI/SCI_ROUT Alarms to SMI/SCI Routing Register

R/W

VSB3

8.4.16

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