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AD9161BBCZ Datasheet(PDF) 127 Page - Analog Devices |
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AD9161BBCZ Datasheet(HTML) 127 Page - Analog Devices |
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127 / 144 page  Data Sheet AD9161/AD9162 Rev. D | Page 127 of 144 Hex. Addr. Name Bits Bit Name Settings Description Reset Access 1 After code group sync is achieved, if a /K/ is followed by any character other than an /R/ or another /K/, QBD asserts SYNCOUT. 1 NO_ILAS This signal must only be programmed while the QBD is held in soft reset (Register 0x475, Bit 3), and must not be changed during normal operation. 0x0 R/W 1 For single-lane operation, ILAS is omitted. Code group sync is followed by user data. 0 Code group sync is followed by ILAS. For multilane operation, NO_ILAS must always be set to 0. 0 FCHK_N Checksum calculation method. This signal must only be programmed while the QBD is held in soft reset (Register 0x475, Register 3), and must not be changed during normal operation. 0x0 R/W 0 Calculate checksum by summing individual fields (this more closely matches the definition of the checksum field in the JESD204B standard. 1 Calculate checksum by summing the registers containing the packed fields (this setting is provided in case the framer of another vendor performs the calculation with this method). 0x477 CTRLREG2 7 ILS_MODE Data link layer test mode. This signal must only be programmed while the QBD is held in soft reset (Register 0x475, Bit 3), and must not be changed during normal operation. 0x0 R/W 0 Normal mode. 1 Code group sync pattern is followed by a perpetual ILAS sequence. 6 RESERVED Reserved. 0x0 R 5 REPDATATEST Repetitive data test enable, using JTSPAT pattern. To enable the test, ILS_MODE must = 0. This signal must only be programmed while the QBD is held in soft reset (Register 0x475, Bit 3), and must not be changed during normal operation. 0x0 R/W 4 QUETESTERR Queue test error mode. This signal must only be programmed while the QBD is held in soft reset (Register 0x475, Bit 3), and must not be changed during normal operation. 0x0 R/W |
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